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utils.py: add more ARM registers

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Signed-off-by: Hector Martin <marcan@marcan.st>
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Hector Martin 2021-01-23 22:33:44 +09:00
parent 7b53b0ae9c
commit 99fb647a9b
1 changed files with 15 additions and 0 deletions
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15
proxyclient/utils.py
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@ -17,6 +17,21 @@ CNTP_TVAL_EL0 = 3,3,14,2,0
CNTP_CTL_EL0 = 3,3,14,2,1 CNTP_CTL_EL0 = 3,3,14,2,1
CNTP_CVAL_EL0 = 3,3,14,2,2 CNTP_CVAL_EL0 = 3,3,14,2,2
SCTLR_EL1 = 3,0,1,0,0
TTBR0_EL1 = 3,0,2,0,0
TTBR0_EL2 = 3,4,2,0,0
TCR_EL1 = 3,0,2,0,2
TCR_EL2 = 3,4,2,0,2
HCR_EL2 = 3,4,1,1,0
MIDR_EL1 = 3,0,0,0,0
MPIDR_EL1 = 3,0,0,0,5
AA64MMFR0_EL1 = 3,0,0,7,0
OSLAR_EL1 = 2,0,1,0,4
ACTLR_EL1 = 3,0,1,0,1
class ProxyUtils(object): class ProxyUtils(object):
def __init__(self, p): def __init__(self, p):
self.iface = p.iface self.iface = p.iface