Mirrors/m1n1
2
0
Fork 0
mirror of https://github.com/AsahiLinux/m1n1 synced 2024-11-28 17:30:18 +00:00
Code Issues Projects Releases Packages Wiki Activity

hv: Use architectural ACTLR_EL12 on M2+

Browse source 
Signed-off-by: Asahi Lina <lina@asahilina.net>
This commit is contained in:
Asahi Lina 2024-09-22 00:49:44 +09:00
parent 83ac04c1a9
commit 99571e5308
6 changed files with 28 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
proxyclient/m1n1/hv/__init__.py
View file

@ -50,7 +50,7 @@ class HV(Reloadable):
MAIR_EL1: MAIR_EL12, MAIR_EL1: MAIR_EL12,
AMAIR_EL1: AMAIR_EL12, AMAIR_EL1: AMAIR_EL12,
CONTEXTIDR_EL1: CONTEXTIDR_EL12, CONTEXTIDR_EL1: CONTEXTIDR_EL12,
ACTLR_EL1: ACTLR_EL12, # ACTLR_EL1: ACTLR_EL12, # Handled in hv_exc.c, depends on CPU version
AMX_CONFIG_EL1: AMX_CONFIG_EL12, AMX_CONFIG_EL1: AMX_CONFIG_EL12,
SPRR_CONFIG_EL1: SPRR_CONFIG_EL12, SPRR_CONFIG_EL1: SPRR_CONFIG_EL12,
SPRR_PPERM_EL1: SPRR_PPERM_EL12, SPRR_PPERM_EL1: SPRR_PPERM_EL12,

1
src/arm_cpu_regs.h
View file

@ -5,6 +5,7 @@
#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
#define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1) #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1)
#define SYS_ACTLR_EL3 sys_reg(3, 6, 1, 0, 1) #define SYS_ACTLR_EL3 sys_reg(3, 6, 1, 0, 1)
#define SYS_ACTLR_EL12 sys_reg(3, 5, 1, 0, 1)
#define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0) #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
// HCR_EL2.E2H == 1 // HCR_EL2.E2H == 1

5
src/chickens.c
View file

@ -42,6 +42,8 @@ void init_t6021_avalanche(int rev);
void init_t6031_sawtooth(void); void init_t6031_sawtooth(void);
void init_t6031_everest(int rev); void init_t6031_everest(int rev);
bool cpufeat_actlr_el2;
const char *init_cpu(void) const char *init_cpu(void)
{ {
const char *cpu = "Unknown"; const char *cpu = "Unknown";
@ -142,6 +144,9 @@ const char *init_cpu(void)
break; break;
} }
if (part >= MIDR_PART_T8110_BLIZZARD)
cpufeat_actlr_el2 = true;
int core = mrs(MPIDR_EL1) & 0xff; int core = mrs(MPIDR_EL1) & 0xff;
// Unknown, related to SMP? // Unknown, related to SMP?

15
src/hv_exc.c
View file

@ -229,7 +229,6 @@ static bool hv_handle_msr_unlocked(struct exc_info *ctx, u64 iss)
SYSREG_PASS(sys_reg(3, 1, 15, 9, 0)); SYSREG_PASS(sys_reg(3, 1, 15, 9, 0));
SYSREG_PASS(sys_reg(3, 1, 15, 10, 0)); SYSREG_PASS(sys_reg(3, 1, 15, 10, 0));
/* Noisy traps */ /* Noisy traps */
SYSREG_MAP(SYS_ACTLR_EL1, SYS_IMP_APL_ACTLR_EL12)
SYSREG_PASS(SYS_IMP_APL_HID4) SYSREG_PASS(SYS_IMP_APL_HID4)
SYSREG_PASS(SYS_IMP_APL_EHID4) SYSREG_PASS(SYS_IMP_APL_EHID4)
/* We don't normally trap hese, but if we do, they're noisy */ /* We don't normally trap hese, but if we do, they're noisy */
@ -272,6 +271,20 @@ static bool hv_handle_msr_unlocked(struct exc_info *ctx, u64 iss)
SYSREG_PASS(sys_reg(1, 0, 8, 1, 2)) // TLBI ASIDE1OS SYSREG_PASS(sys_reg(1, 0, 8, 1, 2)) // TLBI ASIDE1OS
SYSREG_PASS(sys_reg(1, 0, 8, 5, 1)) // TLBI RVAE1OS SYSREG_PASS(sys_reg(1, 0, 8, 5, 1)) // TLBI RVAE1OS
case SYSREG_ISS(SYS_ACTLR_EL1):
if (is_read) {
if (cpufeat_actlr_el2)
regs[rt] = mrs(SYS_ACTLR_EL12);
else
regs[rt] = mrs(SYS_IMP_APL_ACTLR_EL12);
} else {
if (cpufeat_actlr_el2)
msr(SYS_ACTLR_EL12, regs[rt]);
else
msr(SYS_IMP_APL_ACTLR_EL12, regs[rt]);
}
return true;
case SYSREG_ISS(SYS_IMP_APL_IPI_SR_EL1): case SYSREG_ISS(SYS_IMP_APL_IPI_SR_EL1):
if (is_read) if (is_read)
regs[rt] = PERCPU(ipi_pending) ? IPI_SR_PENDING : 0; regs[rt] = PERCPU(ipi_pending) ? IPI_SR_PENDING : 0;

1
src/utils.h
View file

@ -429,6 +429,7 @@ struct vector_args {
}; };
extern u32 board_id, chip_id; extern u32 board_id, chip_id;
extern bool cpufeat_actlr_el2;
extern struct vector_args next_stage; extern struct vector_args next_stage;

5
tools/apple_regs.json
View file

@ -276,7 +276,7 @@
{"index": 0, "name": "SPRR_AMRANGE_EL2", "fullname": "SPRR AM Range (EL2)", "enc": [3, 6, 15, 14, 3 ], "width": 64}, {"index": 0, "name": "SPRR_AMRANGE_EL2", "fullname": "SPRR AM Range (EL2)", "enc": [3, 6, 15, 14, 3 ], "width": 64},
{"index": 0, "name": "VMKEYLO_EL2", "fullname": "Pointer Authentication VM Machine Key Low", "enc": [3, 6, 15, 14, 4 ], "width": 64}, {"index": 0, "name": "VMKEYLO_EL2", "fullname": "Pointer Authentication VM Machine Key Low", "enc": [3, 6, 15, 14, 4 ], "width": 64},
{"index": 0, "name": "VMKEYHI_EL2", "fullname": "Pointer Authentication VM Machine Key High", "enc": [3, 6, 15, 14, 5 ], "width": 64}, {"index": 0, "name": "VMKEYHI_EL2", "fullname": "Pointer Authentication VM Machine Key High", "enc": [3, 6, 15, 14, 5 ], "width": 64},
{"index": 0, "name": "ACTLR_EL12", "fullname": "Auxiliary Control Register (EL12)", "enc": [3, 6, 15, 14, 6 ], "width": 64}, {"index": 0, "name": "ACTLR_EL12_PRE", "fullname": "Auxiliary Control Register (EL12, pre-spec)", "enc": [3, 6, 15, 14, 6 ], "width": 64},
{"index": 0, "name": "APSTS_EL12", "fullname": "Pointer Authentication Status (EL12)", "enc": [3, 6, 15, 14, 7 ], "width": 64}, {"index": 0, "name": "APSTS_EL12", "fullname": "Pointer Authentication Status (EL12)", "enc": [3, 6, 15, 14, 7 ], "width": 64},
{"index": 0, "name": "APCTL_EL12", "fullname": "Pointer Authentication Control (EL12)", "enc": [3, 6, 15, 15, 0 ], "width": 64}, {"index": 0, "name": "APCTL_EL12", "fullname": "Pointer Authentication Control (EL12)", "enc": [3, 6, 15, 15, 0 ], "width": 64},
{"index": 0, "name": "GXF_CONFIG_EL12", "fullname": "GXF Configuration Register (EL12)", "enc": [3, 6, 15, 15, 1 ], "width": 64}, {"index": 0, "name": "GXF_CONFIG_EL12", "fullname": "GXF Configuration Register (EL12)", "enc": [3, 6, 15, 15, 1 ], "width": 64},
@ -332,5 +332,6 @@
{"name": "TRAP_PM", "msb": 57, "lsb": 57}, {"name": "TRAP_PM", "msb": 57, "lsb": 57},
{"name": "TRAP_UPM", "msb": 58, "lsb": 58}, {"name": "TRAP_UPM", "msb": 58, "lsb": 58},
{"name": "TRAP_s3_1z7_c15_cx_3", "msb": 59, "lsb": 59} {"name": "TRAP_s3_1z7_c15_cx_3", "msb": 59, "lsb": 59}
]}]} ]}]},
{"index": 0, "name": "ACTLR_EL12", "fullname": "Auxiliary Control Register (EL12)", "enc": [3, 5, 1, 0, 1 ], "width": 64}
] ]