sysreg.py: Define bitfields for more Apple regs

Signed-off-by: Hector Martin <marcan@marcan.st>

proxyclient/sysreg.py

@@ -150,3 +150,98 @@ class SPSR(Register64):
     F = 6
     M = 4, 0, SPSR_M
 
+class ACTLR(Register64):
+    EnMDSB  = 12
+    EnPRSV  = 6
+    EnAFP   = 5
+    EnAPFLG = 4
+    DisHWP  = 3
+    EnTSO   = 1
+
+class HCR(Register64):
+    TWEDEL   = 63, 60
+    TWEDEn   = 59
+    TID5     = 58
+    DCT      = 57
+    ATA      = 56
+    TTLBOS   = 55
+    TTLBIS   = 54
+    EnSCXT   = 53
+    TOCU     = 52
+    AMVOFFEN = 51
+    TICAB    = 50
+    TID4     = 49
+    FIEN     = 47
+    FWB      = 46
+    NV2      = 45
+    AT       = 44
+    NV1      = 43
+    NV1      = 43
+    NV       = 42
+    NV       = 42
+    API      = 41
+    APK      = 40
+    MIOCNCE  = 38
+    TEA      = 37
+    TERR     = 36
+    TLOR     = 35
+    E2H      = 34
+    ID       = 33
+    CD       = 32
+    RW       = 31
+    TRVM     = 30
+    HCD      = 29
+    TDZ      = 28
+    TGE      = 27
+    TVM      = 26
+    TTLB     = 25
+    TPU      = 24
+    TPCP     = 23
+    TPC      = 23
+    TSW      = 22
+    TACR     = 21
+    TIDCP    = 20
+    TSC      = 19
+    TID3     = 18
+    TID2     = 17
+    TID1     = 16
+    TID0     = 15
+    TWE      = 14
+    TWI      = 13
+    DC       = 12
+    BSU      = 11, 10
+    FB       = 9
+    VSE      = 8
+    VI       = 7
+    VF       = 6
+    AMO      = 5
+    IMO      = 4
+    FMO      = 3
+    PTW      = 2
+    SWIO     = 1
+    VM       = 0
+
+class HACR(Register64):
+    TRAP_CPU_EXT = 0
+    TRAP_AIDR = 4
+    TRAP_AMX = 10
+    TRAP_SPRR = 11
+    TRAP_GXF = 13
+    TRAP_CTRR = 14
+    TRAP_IPI = 16
+    TRAP_s3_4_c15_c5z6_x = 18
+    TRAP_s3_4_c15_c0z12_5 = 19
+    GIC_CNTV = 20
+    TRAP_s3_4_c15_c10_4 = 25
+    TRAP_SERROR_INFO = 48
+    TRAP_EHID = 49
+    TRAP_HID = 50
+    TRAP_s3_0_c15_c12_1z2 = 51
+    TRAP_ACC = 52
+    TRAP_PM = 57
+    TRAP_UPM = 58
+    TRAP_s3_1z7_c15_cx_3 = 59
+
+class AMX_CTL(Register64):
+    EN = 63
+    EN_EL1 = 62