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https://github.com/AsahiLinux/m1n1
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fb: Map the framebuffer uncached, and use a shadow FB for speed
Turns out AMCC on t600x throws errors when DISP0 real-time memory requests hit the CPU cache, and then macOS panics. Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin
parent
dc3806252b
commit
8fa422c0d3
5 changed files with 40 additions and 10 deletions
31
src/fb.c
31
src/fb.c
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@ -65,13 +65,18 @@ const struct image logo_256 = {
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const struct image *logo;
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struct image orig_logo;
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void fb_update(void)
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{
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memcpy(fb.hwptr, fb.ptr, fb.size);
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}
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static void fb_clear_font_row(u32 row)
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{
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const u32 row_size = (console.margin.cols + console.cursor.max_col) * console.font.width * 4;
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const u32 ystart = (console.margin.rows + row) * console.font.height * fb.stride;
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for (u32 y = 0; y < console.font.height; ++y)
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memset(fb.ptr + ystart + y * fb.stride, 0, row_size);
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memset32(fb.ptr + ystart + y * fb.stride, 0, row_size);
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}
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static void fb_move_font_row(u32 dst, u32 src)
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@ -84,7 +89,7 @@ static void fb_move_font_row(u32 dst, u32 src)
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ydst *= fb.stride;
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for (u32 y = 0; y < console.font.height; ++y)
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memcpy(fb.ptr + ydst + y * fb.stride, fb.ptr + ysrc + y * fb.stride, row_size);
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memcpy32(fb.ptr + ydst + y * fb.stride, fb.ptr + ysrc + y * fb.stride, row_size);
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fb_clear_font_row(src);
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}
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@ -121,6 +126,7 @@ void fb_blit(u32 x, u32 y, u32 w, u32 h, void *data, u32 stride)
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fb_set_pixel(x + j, y + i, color);
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}
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}
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fb_update();
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}
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void fb_unblit(u32 x, u32 y, u32 w, u32 h, void *data, u32 stride)
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@ -143,12 +149,14 @@ void fb_fill(u32 x, u32 y, u32 w, u32 h, rgb_t color)
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u32 c = rgb2pixel_30(color);
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for (u32 i = 0; i < h; i++)
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memset32(&fb.ptr[x + (y + i) * fb.stride], c, w * 4);
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fb_update();
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}
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void fb_clear(rgb_t color)
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{
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u32 c = rgb2pixel_30(color);
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memset32(fb.ptr, c, fb.stride * fb.height * 4);
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fb_update();
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}
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void fb_blit_image(u32 x, u32 y, const struct image *img)
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@ -253,6 +261,7 @@ void fb_console_reserve_lines(u32 n)
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{
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if ((console.cursor.max_row - console.cursor.row) <= n)
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fb_console_scroll(1 + n - (console.cursor.max_row - console.cursor.row));
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fb_update();
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}
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ssize_t fb_console_write(const char *bfr, size_t len)
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@ -267,6 +276,8 @@ ssize_t fb_console_write(const char *bfr, size_t len)
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wrote++;
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}
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fb_update();
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return wrote;
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}
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@ -296,20 +307,27 @@ static void fb_clear_console(void)
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{
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for (u32 row = 0; row < console.cursor.max_row; ++row)
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fb_clear_font_row(row);
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console.cursor.col = 0;
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console.cursor.row = 0;
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fb_update();
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}
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void fb_init(void)
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{
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fb.ptr = (void *)cur_boot_args.video.base;
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fb.hwptr = (void *)cur_boot_args.video.base;
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fb.stride = cur_boot_args.video.stride / 4;
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fb.width = cur_boot_args.video.width;
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fb.height = cur_boot_args.video.height;
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fb.depth = cur_boot_args.video.depth & FB_DEPTH_MASK;
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fb.size = cur_boot_args.video.stride * cur_boot_args.video.height;
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printf("fb init: %dx%d (%d) [s=%d] @%p\n", fb.width, fb.height, fb.depth, fb.stride, fb.ptr);
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uint64_t fb_size = cur_boot_args.video.stride * cur_boot_args.video.height;
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mmu_add_mapping(cur_boot_args.video.base, cur_boot_args.video.base, ALIGN_UP(fb_size, 0x4000),
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MAIR_IDX_NORMAL, PERM_RWX);
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mmu_add_mapping(cur_boot_args.video.base, cur_boot_args.video.base, ALIGN_UP(fb.size, 0x4000),
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MAIR_IDX_FRAMEBUFFER, PERM_RW);
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fb.ptr = malloc(fb.size);
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memcpy(fb.ptr, fb.hwptr, fb.size);
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if (cur_boot_args.video.depth & FB_DEPTH_FLAG_RETINA) {
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logo = &logo_256;
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@ -359,4 +377,5 @@ void fb_shutdown(bool restore_logo)
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free(orig_logo.ptr);
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orig_logo.ptr = NULL;
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}
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free(fb.ptr);
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}
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3
src/fb.h
3
src/fb.h
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@ -7,10 +7,12 @@
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typedef struct {
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u32 *ptr; /* pointer to the start of the framebuffer */
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u32 *hwptr; /* pointer to the start of the real framebuffer */
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u32 stride; /* framebuffer stride divided by four (i.e. stride in pixels) */
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u32 depth; /* framebuffer depth (i.e. bits per pixel) */
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u32 width; /* width of the framebuffer in pixels */
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u32 height; /* height of the framebuffer in pixels */
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u32 size; /* size of the framebuffer in bytes */
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} fb_t;
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typedef struct {
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@ -28,6 +30,7 @@ static inline rgb_t int2rgb(u32 c)
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void fb_init(void);
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void fb_shutdown(bool restore_logo);
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void fb_update(void);
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void fb_blit(u32 x, u32 y, u32 w, u32 h, void *data, u32 stride);
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void fb_unblit(u32 x, u32 y, u32 w, u32 h, void *data, u32 stride);
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@ -106,10 +106,10 @@ void m1n1_main(void)
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exception_shutdown();
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usb_iodev_shutdown();
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mmu_shutdown();
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#ifdef USE_FB
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fb_shutdown(next_stage.restore_logo);
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#endif
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mmu_shutdown();
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printf("Vectoring to next stage...\n");
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10
src/memory.c
10
src/memory.c
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@ -149,6 +149,7 @@ enum SPRR_val_t {
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#define MAIR_SHIFT_NORMAL (MAIR_IDX_NORMAL * 8)
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#define MAIR_SHIFT_DEVICE_nGnRnE (MAIR_IDX_DEVICE_nGnRnE * 8)
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#define MAIR_SHIFT_DEVICE_nGnRE (MAIR_IDX_DEVICE_nGnRE * 8)
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#define MAIR_SHIFT_FRAMEBUFFER (MAIR_IDX_FRAMEBUFFER * 8)
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/*
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* https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/memory-attribute-indirection-register--el1
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@ -161,6 +162,7 @@ enum SPRR_val_t {
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#define MAIR_ATTR_NORMAL_DEFAULT 0xffUL
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#define MAIR_ATTR_DEVICE_nGnRnE 0x00UL
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#define MAIR_ATTR_DEVICE_nGnRE 0x04UL
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#define MAIR_ATTR_FRAMEBUFFER 0x44UL
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static u64 mmu_pt_L0[2] ALIGNED(PAGE_SIZE);
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static u64 mmu_pt_L1[ENTRIES_PER_L1_TABLE] ALIGNED(PAGE_SIZE);
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@ -299,8 +301,9 @@ static void mmu_init_pagetables(void)
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void mmu_add_mapping(u64 from, u64 to, size_t size, u8 attribute_index, u64 perms)
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{
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if (mmu_map(from, to | PTE_MAIR_IDX(attribute_index) | PTE_ACCESS | PTE_VALID | perms, size) <
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0)
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if (mmu_map(from,
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to | PTE_MAIR_IDX(attribute_index) | PTE_ACCESS | PTE_VALID | PTE_SH_OS | perms,
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size) < 0)
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panic("Failed to add MMU mapping 0x%lx -> 0x%lx (0x%lx)\n", from, to, size);
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sysop("dsb ishst");
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@ -473,7 +476,8 @@ static void mmu_configure(void)
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{
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msr(MAIR_EL1, (MAIR_ATTR_NORMAL_DEFAULT << MAIR_SHIFT_NORMAL) |
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(MAIR_ATTR_DEVICE_nGnRnE << MAIR_SHIFT_DEVICE_nGnRnE) |
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(MAIR_ATTR_DEVICE_nGnRE << MAIR_SHIFT_DEVICE_nGnRE));
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(MAIR_ATTR_DEVICE_nGnRE << MAIR_SHIFT_DEVICE_nGnRE) |
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(MAIR_ATTR_FRAMEBUFFER << MAIR_SHIFT_FRAMEBUFFER));
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msr(TCR_EL1, FIELD_PREP(TCR_IPS, TCR_IPS_4TB) | FIELD_PREP(TCR_TG1, TCR_TG1_16K) |
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FIELD_PREP(TCR_SH1, TCR_SH1_IS) | FIELD_PREP(TCR_ORGN1, TCR_ORGN1_WBWA) |
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FIELD_PREP(TCR_IRGN1, TCR_IRGN1_WBWA) | FIELD_PREP(TCR_T1SZ, TCR_T1SZ_48BIT) |
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@ -29,6 +29,9 @@
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#define PTE_UXN BIT(54)
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#define PTE_AP_RO BIT(7)
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#define PTE_AP_EL0 BIT(6)
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#define PTE_SH_NS (0b00 << 8)
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#define PTE_SH_OS (0b10 << 8)
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#define PTE_SH_IS (0b11 << 8)
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#define PERM_RO_EL0 PTE_AP_EL0 | PTE_AP_RO | PTE_PXN | PTE_UXN
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#define PERM_RW_EL0 PTE_AP_EL0 | PTE_PXN | PTE_UXN
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@ -43,6 +46,7 @@
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#define MAIR_IDX_NORMAL 0
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#define MAIR_IDX_DEVICE_nGnRnE 1
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#define MAIR_IDX_DEVICE_nGnRE 2
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#define MAIR_IDX_FRAMEBUFFER 3
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#ifndef __ASSEMBLER__
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