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https://github.com/AsahiLinux/m1n1
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pcie: T602X APCIE-GE support
Maybe maybe? Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin
parent
721107aa0a
commit
8e3016e323
1 changed files with 315 additions and 174 deletions
489
src/pcie.c
489
src/pcie.c
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@ -3,6 +3,7 @@
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#include "adt.h"
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#include "pcie.h"
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#include "pmgr.h"
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#include "string.h"
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#include "tunables.h"
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#include "utils.h"
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@ -98,6 +99,9 @@
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#define DWC_DBI_LINK_WIDTH GENMASK(12, 8)
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#define DWC_DBI_SPEED_CHANGE BIT(17)
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#define PHY_STRIDE 0x4000
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#define PHYIP_STRIDE 0x40000
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struct fuse_bits {
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u16 src_reg;
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u16 tgt_reg;
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@ -174,27 +178,45 @@ static const struct reg_info regs_t602x = {
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};
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static bool pcie_initialized = false;
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static u64 rc_base;
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static u64 phy_common_base;
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static u64 phy_base;
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static u64 phy_ip_base;
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static u64 fuse_base;
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static u32 port_count;
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static u64 port_base[8];
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static u64 port_ltssm_base[8];
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static u64 port_phy_base[8];
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static u64 port_intr2axi_base[8];
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static const struct reg_info *pcie_regs;
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int pcie_init(void)
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enum PCIE_CONTROLLERS {
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APCIE,
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APCIE_GE0,
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APCIE_GE1,
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NUM_CONTROLLERS,
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};
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#define MAX_PHYS 4
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struct state {
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int num_phys;
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u64 rc_base;
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u64 phy_common_base;
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u64 phy_base[MAX_PHYS];
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u64 phy_ip_base[MAX_PHYS];
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u64 fuse_base;
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u32 port_count;
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u64 port_base[8];
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u64 port_ltssm_base[8];
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u64 port_phy_base[8];
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u64 port_intr2axi_base[8];
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const struct reg_info *pcie_regs;
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bool initialized;
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};
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static struct state controllers[NUM_CONTROLLERS];
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static int pcie_init_controller(int controller, const char *path)
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{
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const char *path = "/arm-io/apcie";
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struct state *state = &controllers[controller];
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int adt_path[8];
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int adt_offset;
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u32 lane_mode = DWC_DBI_PORT_LINK_MODE_1_LANE;
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u32 link_width = 1;
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const struct fuse_bits *fuse_bits;
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if (pcie_initialized)
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return 0;
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state->initialized = false;
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state->num_phys = 1;
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adt_offset = adt_path_offset_trace(adt, path, adt_path);
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if (adt_offset < 0) {
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@ -204,62 +226,97 @@ int pcie_init(void)
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if (adt_is_compatible(adt, adt_offset, "apcie,t8103")) {
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fuse_bits = pcie_fuse_bits_t8103;
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pcie_regs = ®s_t8xxx_t600x;
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state->pcie_regs = ®s_t8xxx_t600x;
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printf("pcie: Initializing t8103 PCIe controller\n");
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} else if (adt_is_compatible(adt, adt_offset, "apcie,t6000")) {
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fuse_bits = pcie_fuse_bits_t6000;
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pcie_regs = ®s_t8xxx_t600x;
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state->pcie_regs = ®s_t8xxx_t600x;
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printf("pcie: Initializing t6000 PCIe controller\n");
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} else if (adt_is_compatible(adt, adt_offset, "apcie,t8112")) {
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fuse_bits = pcie_fuse_bits_t8112;
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pcie_regs = ®s_t8xxx_t600x;
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state->pcie_regs = ®s_t8xxx_t600x;
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printf("pcie: Initializing t8112 PCIe controller\n");
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} else if (adt_is_compatible(adt, adt_offset, "apcie,t6020")) {
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fuse_bits = NULL;
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pcie_regs = ®s_t602x;
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state->pcie_regs = ®s_t602x;
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printf("pcie: Initializing t6020 PCIe controller\n");
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} else if (adt_is_compatible(adt, adt_offset, "apcie-ge,t6020")) {
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u32 lane_cfg;
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fuse_bits = NULL;
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state->pcie_regs = ®s_t602x;
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printf("pcie: Initializing t6020 PCIe GE controller\n");
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if (ADT_GETPROP(adt, adt_offset, "lane-cfg", &lane_cfg) < 0) {
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printf("pcie: Error getting lane_cfg for %s\n", path);
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return -1;
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}
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switch (lane_cfg) {
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case 0:
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state->num_phys = 4;
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lane_mode = DWC_DBI_PORT_LINK_MODE_16_LANES;
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link_width = 16;
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break;
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case 1:
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state->num_phys = 2;
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lane_mode = DWC_DBI_PORT_LINK_MODE_8_LANES;
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link_width = 8;
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break;
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default:
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printf("pcie: Unknown lane config %d for %s\n", lane_cfg, path);
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return -1;
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}
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} else {
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printf("pcie: Unsupported compatible\n");
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return -1;
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}
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if (ADT_GETPROP(adt, adt_offset, "#ports", &port_count) < 0) {
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if (ADT_GETPROP(adt, adt_offset, "#ports", &state->port_count) < 0) {
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printf("pcie: Error getting port count for %s\n", path);
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return -1;
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}
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u64 config_base;
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if (adt_get_reg(adt, adt_path, "reg", pcie_regs->config_idx, &config_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", pcie_regs->config_idx, path);
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if (adt_get_reg(adt, adt_path, "reg", state->pcie_regs->config_idx, &config_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", state->pcie_regs->config_idx,
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path);
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return -1;
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}
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if (adt_get_reg(adt, adt_path, "reg", pcie_regs->rc_idx, &rc_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", pcie_regs->rc_idx, path);
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if (adt_get_reg(adt, adt_path, "reg", state->pcie_regs->rc_idx, &state->rc_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", state->pcie_regs->rc_idx, path);
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return -1;
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}
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if (pcie_regs->phy_common_idx != -1) {
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if (adt_get_reg(adt, adt_path, "reg", pcie_regs->phy_common_idx, &phy_common_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", pcie_regs->phy_idx, path);
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if (state->pcie_regs->phy_common_idx != -1) {
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if (adt_get_reg(adt, adt_path, "reg", state->pcie_regs->phy_common_idx,
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&state->phy_common_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", state->pcie_regs->phy_idx,
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path);
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return -1;
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}
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} else {
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phy_common_base = 0;
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state->phy_common_base = 0;
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}
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if (adt_get_reg(adt, adt_path, "reg", pcie_regs->phy_idx, &phy_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", pcie_regs->phy_idx, path);
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if (adt_get_reg(adt, adt_path, "reg", state->pcie_regs->phy_idx, &state->phy_base[0], NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", state->pcie_regs->phy_idx, path);
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return -1;
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}
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if (adt_get_reg(adt, adt_path, "reg", pcie_regs->phy_ip_idx, &phy_ip_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", pcie_regs->phy_ip_idx, path);
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if (adt_get_reg(adt, adt_path, "reg", state->pcie_regs->phy_ip_idx, &state->phy_ip_base[0],
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NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", state->pcie_regs->phy_ip_idx,
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path);
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return -1;
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}
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if (adt_get_reg(adt, adt_path, "reg", pcie_regs->fuse_idx, &fuse_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", pcie_regs->fuse_idx, path);
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for (int phy = 1; phy < state->num_phys; phy++) {
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state->phy_base[phy] = state->phy_base[0] + PHY_STRIDE * phy;
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state->phy_ip_base[phy] = state->phy_ip_base[0] + PHYIP_STRIDE * phy;
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}
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if (adt_get_reg(adt, adt_path, "reg", state->pcie_regs->fuse_idx, &state->fuse_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", state->pcie_regs->fuse_idx, path);
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return -1;
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}
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@ -269,15 +326,15 @@ int pcie_init(void)
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return -1;
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}
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int port_regs = (reg_len / 16) - pcie_regs->shared_reg_count;
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int port_regs = (reg_len / 16) - state->pcie_regs->shared_reg_count;
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if (port_regs % port_count) {
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if (port_regs % state->port_count) {
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printf("pcie: %d port registers do not evenly divide into %d ports\n", port_regs,
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port_count);
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state->port_count);
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return -1;
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}
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int port_reg_cnt = port_regs / port_count;
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int port_reg_cnt = port_regs / state->port_count;
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printf("pcie: ADT uses %d reg entries per port\n", port_reg_cnt);
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if (pmgr_adt_power_enable(path)) {
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@ -285,17 +342,18 @@ int pcie_init(void)
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return -1;
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}
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if (tunables_apply_local(path, "apcie-axi2af-tunables", pcie_regs->axi_idx)) {
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if (tunables_apply_local(path, "apcie-axi2af-tunables", state->pcie_regs->axi_idx)) {
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printf("pcie: Error applying %s for %s\n", "apcie-axi2af-tunables", path);
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return -1;
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}
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/* ??? */
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write32(rc_base + 0x4, 0);
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if (controller == APCIE)
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write32(state->rc_base + 0x4, 0);
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if (!adt_getprop(adt, adt_offset, "apcie-common-tunables", NULL)) {
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printf("pcie: No common tunables\n");
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} else if (tunables_apply_local(path, "apcie-common-tunables", pcie_regs->rc_idx)) {
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} else if (tunables_apply_local(path, "apcie-common-tunables", state->pcie_regs->rc_idx)) {
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printf("pcie: Error applying %s for %s\n", "apcie-common-tunables", path);
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return -1;
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}
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@ -306,81 +364,105 @@ int pcie_init(void)
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if (!adt_getprop(adt, adt_offset, "apcie-phy-tunables", NULL)) {
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printf("pcie: No PHY tunables\n");
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} else if (tunables_apply_local(path, "apcie-phy-tunables", pcie_regs->phy_idx)) {
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} else if (tunables_apply_local(path, "apcie-phy-tunables", state->pcie_regs->phy_idx)) {
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printf("pcie: Error applying %s for %s\n", "apcie-phy-tunables", path);
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return -1;
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}
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if (pcie_regs->type == APCIE_T602X) {
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if (poll32(phy_common_base + APCIE_PHYCMN_CLK, APCIE_PHYCMN_CLK_100MHZ,
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if (state->pcie_regs->type == APCIE_T602X) {
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if (poll32(state->phy_common_base + APCIE_PHYCMN_CLK, APCIE_PHYCMN_CLK_100MHZ,
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APCIE_PHYCMN_CLK_100MHZ, 250000)) {
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printf("pcie: Reference clock not available\n");
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return -1;
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}
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}
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set32(phy_base + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK0REQ);
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if (poll32(phy_base + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK0ACK, APCIE_PHY_CTRL_CLK0ACK, 50000)) {
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printf("pcie: Timeout enabling PHY CLK0\n");
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return -1;
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}
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for (int phy = 0; phy < state->num_phys; phy++) {
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set32(state->phy_base[phy] + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK0REQ);
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if (poll32(state->phy_base[phy] + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK0ACK,
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APCIE_PHY_CTRL_CLK0ACK, 50000)) {
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printf("pcie: Timeout enabling PHY CLK0\n");
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return -1;
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}
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set32(phy_base + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK1REQ);
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if (poll32(phy_base + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK1ACK, APCIE_PHY_CTRL_CLK1ACK, 50000)) {
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printf("pcie: Timeout enabling PHY CLK1\n");
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return -1;
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}
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set32(state->phy_base[phy] + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK1REQ);
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if (poll32(state->phy_base[phy] + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK1ACK,
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APCIE_PHY_CTRL_CLK1ACK, 50000)) {
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printf("pcie: Timeout enabling PHY CLK1\n");
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return -1;
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}
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clear32(phy_base + APCIE_PHY_CTRL, APCIE_PHY_CTRL_RESET);
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udelay(1);
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/* ??? */
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if (pcie_regs->type == APCIE_T81XX) {
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set32(rc_base + APCIE_PHYIF_CTRL, APCIE_PHYIF_CTRL_RUN);
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clear32(state->phy_base[phy] + APCIE_PHY_CTRL, APCIE_PHY_CTRL_RESET);
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udelay(1);
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} else if (pcie_regs->type == APCIE_T602X) {
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set32(phy_base + 4, 0x01);
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/* ??? */
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if (state->pcie_regs->type == APCIE_T81XX) {
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set32(state->rc_base + APCIE_PHYIF_CTRL, APCIE_PHYIF_CTRL_RUN);
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udelay(1);
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} else if (state->pcie_regs->type == APCIE_T602X) {
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set32(state->phy_base[phy] + 4, 0x01);
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}
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/* Apply "fuses". */
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for (int i = 0; fuse_bits && fuse_bits[i].width; i++) {
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u32 fuse;
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fuse = (read32(state->fuse_base + fuse_bits[i].src_reg) >> fuse_bits[i].src_bit);
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fuse &= (1 << fuse_bits[i].width) - 1;
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mask32(state->phy_ip_base[phy] + fuse_bits[i].tgt_reg,
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((1 << fuse_bits[i].width) - 1) << fuse_bits[i].tgt_bit,
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fuse << fuse_bits[i].tgt_bit);
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}
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char pll_prop[64];
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char auspma_prop[64];
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if (state->num_phys == 1) {
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strcpy(pll_prop, "apcie-phy-ip-pll-tunables");
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strcpy(auspma_prop, "apcie-phy-ip-auspma-tunables");
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} else {
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snprintf(pll_prop, sizeof(pll_prop), "apcie-phy-%d-ip-pll-tunables", phy);
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snprintf(auspma_prop, sizeof(auspma_prop), "apcie-phy-%d-ip-auspma-tunables", phy);
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}
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if (tunables_apply_local_addr(path, pll_prop, state->phy_ip_base[phy])) {
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printf("pcie: Error applying %s for %s\n", pll_prop, path);
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return -1;
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}
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if (tunables_apply_local_addr(path, auspma_prop, state->phy_ip_base[phy])) {
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printf("pcie: Error applying %s for %s\n", auspma_prop, path);
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return -1;
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}
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if (state->pcie_regs->type == APCIE_T602X) {
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set32(state->phy_base[phy] + 4, 0x10);
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}
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}
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/* Apply "fuses". */
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for (int i = 0; fuse_bits && fuse_bits[i].width; i++) {
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u32 fuse;
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fuse = (read32(fuse_base + fuse_bits[i].src_reg) >> fuse_bits[i].src_bit);
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fuse &= (1 << fuse_bits[i].width) - 1;
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mask32(phy_ip_base + fuse_bits[i].tgt_reg,
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((1 << fuse_bits[i].width) - 1) << fuse_bits[i].tgt_bit,
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fuse << fuse_bits[i].tgt_bit);
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}
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if (tunables_apply_local(path, "apcie-phy-ip-pll-tunables", pcie_regs->phy_ip_idx)) {
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printf("pcie: Error applying %s for %s\n", "apcie-phy-ip-pll-tunables", path);
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return -1;
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}
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if (tunables_apply_local(path, "apcie-phy-ip-auspma-tunables", pcie_regs->phy_ip_idx)) {
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printf("pcie: Error applying %s for %s\n", "apcie-phy-ip-auspma-tunables", path);
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return -1;
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}
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if (pcie_regs->type == APCIE_T602X) {
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set32(phy_base + 4, 0x10);
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mask32(phy_common_base + APCIE_PHYCMN_CLK, APCIE_PHYCMN_CLK_MODE,
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if (state->pcie_regs->type == APCIE_T602X) {
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mask32(state->phy_common_base + APCIE_PHYCMN_CLK, APCIE_PHYCMN_CLK_MODE,
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FIELD_PREP(APCIE_PHYCMN_CLK_MODE, 1));
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if (poll32(phy_base + 0x8, 1, 1, 250000)) {
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// Why always PHY 1 in this case?
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u32 off = state->num_phys > 1 ? PHY_STRIDE : 0;
|
||||
if (poll32(state->phy_base[0] + off + 0x8, 1, 1, 250000)) {
|
||||
printf("pcie: PHY clock enable timed out\n");
|
||||
return -1;
|
||||
}
|
||||
set32(phy_base + APCIE_PHY_CTRL, 0x300);
|
||||
write32(rc_base + 0x54, 0x140);
|
||||
write32(rc_base + 0x50, 0x1);
|
||||
if (poll32(rc_base + 0x58, 1, 1, 250000)) {
|
||||
for (int phy = 0; phy < state->num_phys; phy++) {
|
||||
set32(state->phy_base[phy] + APCIE_PHY_CTRL, 0x300);
|
||||
}
|
||||
write32(state->rc_base + 0x54, 0x140);
|
||||
write32(state->rc_base + 0x50, 0x1);
|
||||
if (poll32(state->rc_base + 0x58, 1, 1, 250000)) {
|
||||
printf("pcie: Failed to initialize RC thing\n");
|
||||
return -1;
|
||||
}
|
||||
clear32(rc_base + 0x3c, 0x1);
|
||||
if (controller == APCIE)
|
||||
clear32(state->rc_base + 0x3c, 0x1);
|
||||
pmgr_adt_power_disable_index(path, 1);
|
||||
}
|
||||
|
||||
for (u32 port = 0; port < port_count; port++) {
|
||||
for (u32 port = 0; port < state->port_count; port++) {
|
||||
char bridge[64];
|
||||
int bridge_offset;
|
||||
|
||||
|
|
@ -388,136 +470,166 @@ int pcie_init(void)
|
|||
* Initialize RC port.
|
||||
*/
|
||||
|
||||
snprintf(bridge, sizeof(bridge), "/arm-io/apcie/pci-bridge%d", port);
|
||||
switch (controller) {
|
||||
case APCIE:
|
||||
snprintf(bridge, sizeof(bridge), "/arm-io/apcie/pci-bridge%d", port);
|
||||
break;
|
||||
case APCIE_GE0:
|
||||
strcpy(bridge, "/arm-io/apcie-ge0/pci-ge0-bridge");
|
||||
break;
|
||||
case APCIE_GE1:
|
||||
strcpy(bridge, "/arm-io/apcie-ge1/pci-ge1-bridge");
|
||||
break;
|
||||
}
|
||||
|
||||
if ((bridge_offset = adt_path_offset(adt, bridge)) < 0)
|
||||
continue;
|
||||
|
||||
printf("pcie: Initializing port %d\n", port);
|
||||
|
||||
if (adt_get_reg(adt, adt_path, "reg", port * port_reg_cnt + pcie_regs->shared_reg_count,
|
||||
&port_base[port], NULL)) {
|
||||
if (adt_get_reg(adt, adt_path, "reg",
|
||||
port * port_reg_cnt + state->pcie_regs->shared_reg_count,
|
||||
&state->port_base[port], NULL)) {
|
||||
printf("pcie: Error getting reg with index %d for %s\n",
|
||||
port * port_reg_cnt + pcie_regs->shared_reg_count, path);
|
||||
port * port_reg_cnt + state->pcie_regs->shared_reg_count, path);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (adt_get_reg(adt, adt_path, "reg", port * port_reg_cnt + pcie_regs->shared_reg_count + 1,
|
||||
&port_ltssm_base[port], NULL)) {
|
||||
if (adt_get_reg(adt, adt_path, "reg",
|
||||
port * port_reg_cnt + state->pcie_regs->shared_reg_count + 1,
|
||||
&state->port_ltssm_base[port], NULL)) {
|
||||
printf("pcie: Error getting reg with index %d for %s\n",
|
||||
port * port_reg_cnt + pcie_regs->shared_reg_count + 1, path);
|
||||
port * port_reg_cnt + state->pcie_regs->shared_reg_count + 1, path);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (adt_get_reg(adt, adt_path, "reg", port * port_reg_cnt + pcie_regs->shared_reg_count + 2,
|
||||
&port_phy_base[port], NULL)) {
|
||||
if (adt_get_reg(adt, adt_path, "reg",
|
||||
port * port_reg_cnt + state->pcie_regs->shared_reg_count + 2,
|
||||
&state->port_phy_base[port], NULL)) {
|
||||
printf("pcie: Error getting reg with index %d for %s\n",
|
||||
port * port_reg_cnt + pcie_regs->shared_reg_count + 2, path);
|
||||
port * port_reg_cnt + state->pcie_regs->shared_reg_count + 2, path);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (port_reg_cnt >= 5) {
|
||||
if (adt_get_reg(adt, adt_path, "reg",
|
||||
port * port_reg_cnt + pcie_regs->shared_reg_count + 4,
|
||||
&port_intr2axi_base[port], NULL)) {
|
||||
port * port_reg_cnt + state->pcie_regs->shared_reg_count + 4,
|
||||
&state->port_intr2axi_base[port], NULL)) {
|
||||
printf("pcie: Error getting reg with index %d for %s\n",
|
||||
port * port_reg_cnt + pcie_regs->shared_reg_count + 4, path);
|
||||
port * port_reg_cnt + state->pcie_regs->shared_reg_count + 4, path);
|
||||
return -1;
|
||||
}
|
||||
} else {
|
||||
port_intr2axi_base[port] = 0;
|
||||
state->port_intr2axi_base[port] = 0;
|
||||
}
|
||||
|
||||
if (pcie_regs->type == APCIE_T602X) {
|
||||
set32(rc_base + 0x3c, 0x1);
|
||||
if (state->pcie_regs->type == APCIE_T602X) {
|
||||
set32(state->rc_base + 0x3c, 0x1);
|
||||
|
||||
// ??????
|
||||
write32(port_base[port] + 0x10, 0x2);
|
||||
write32(port_base[port] + 0x88, 0x110);
|
||||
write32(port_base[port] + 0x100, 0xffffffff);
|
||||
write32(port_base[port] + 0x148, 0xffffffff);
|
||||
write32(port_base[port] + 0x210, 0xffffffff);
|
||||
write32(port_base[port] + 0x80, 0x0);
|
||||
write32(port_base[port] + 0x84, 0x0);
|
||||
write32(port_base[port] + 0x104, 0x7fffffff);
|
||||
write32(port_base[port] + 0x124, 0x100);
|
||||
write32(port_base[port] + 0x16c, 0x0);
|
||||
write32(port_base[port] + 0x13c, 0x10);
|
||||
write32(port_base[port] + 0x800, 0x100100);
|
||||
write32(port_base[port] + 0x808, 0x1000ff);
|
||||
write32(port_base[port] + 0x82c, 0x0);
|
||||
if (controller == APCIE)
|
||||
write32(state->port_base[port] + 0x10, 0x2);
|
||||
write32(state->port_base[port] + 0x88, 0x110);
|
||||
write32(state->port_base[port] + 0x100, 0xffffffff);
|
||||
write32(state->port_base[port] + 0x148, 0xffffffff);
|
||||
write32(state->port_base[port] + 0x210, 0xffffffff);
|
||||
write32(state->port_base[port] + 0x80, 0x0);
|
||||
write32(state->port_base[port] + 0x84, 0x0);
|
||||
write32(state->port_base[port] + 0x104, 0x7fffffff);
|
||||
write32(state->port_base[port] + 0x124, 0x100);
|
||||
write32(state->port_base[port] + 0x16c, 0x0);
|
||||
write32(state->port_base[port] + 0x13c, 0x10);
|
||||
write32(state->port_base[port] + 0x800, 0x100100);
|
||||
write32(state->port_base[port] + 0x808, 0x1000ff);
|
||||
write32(state->port_base[port] + 0x82c, 0x0);
|
||||
for (int i = 0; i < 512; i++)
|
||||
write32(port_base[port] + APCIE_T602X_PORT_MSIMAP + 4 * i, 0);
|
||||
write32(port_base[port] + 0x397c, 0x0);
|
||||
write32(port_base[port] + 0x130, 0x3000000);
|
||||
write32(port_base[port] + 0x140, 0x10);
|
||||
write32(port_base[port] + 0x144, 0x253770);
|
||||
write32(port_base[port] + 0x21c, 0x0);
|
||||
write32(port_base[port] + 0x834, 0x0);
|
||||
write32(state->port_base[port] + APCIE_T602X_PORT_MSIMAP + 4 * i, 0);
|
||||
write32(state->port_base[port] + 0x397c, 0x0);
|
||||
if (controller == APCIE)
|
||||
write32(state->port_base[port] + 0x130, 0x3000000);
|
||||
else
|
||||
write32(state->port_base[port] + 0x130, 0x3000008);
|
||||
write32(state->port_base[port] + 0x140, 0x10);
|
||||
write32(state->port_base[port] + 0x144, 0x253770);
|
||||
write32(state->port_base[port] + 0x21c, 0x0);
|
||||
write32(state->port_base[port] + 0x834, 0x0);
|
||||
if (controller != APCIE)
|
||||
write32(state->port_base[port] + 0x83c, 0x0);
|
||||
}
|
||||
|
||||
if (tunables_apply_local_addr(bridge, "apcie-config-tunables", port_base[port])) {
|
||||
if (tunables_apply_local_addr(bridge, "apcie-config-tunables", state->port_base[port])) {
|
||||
printf("pcie: Error applying %s for %s\n", "apcie-config-tunables", bridge);
|
||||
return -1;
|
||||
}
|
||||
|
||||
set32(port_base[port] + APCIE_PORT_APPCLK, APCIE_PORT_APPCLK_EN);
|
||||
set32(state->port_base[port] + APCIE_PORT_APPCLK, APCIE_PORT_APPCLK_EN);
|
||||
|
||||
if (pcie_regs->type == APCIE_T602X) {
|
||||
clear32(port_phy_base[port] + APCIE_PHY_CTRL,
|
||||
if (state->pcie_regs->type == APCIE_T602X) {
|
||||
clear32(state->port_phy_base[port] + APCIE_PHY_CTRL,
|
||||
APCIE_PHY_CTRL_CLK0REQ | APCIE_PHY_CTRL_CLK1REQ);
|
||||
|
||||
set32(port_phy_base[port] + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK0REQ);
|
||||
if (poll32(port_phy_base[port] + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK0ACK,
|
||||
set32(state->port_phy_base[port] + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK0REQ);
|
||||
if (poll32(state->port_phy_base[port] + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK0ACK,
|
||||
APCIE_PHY_CTRL_CLK0ACK, 50000)) {
|
||||
printf("pcie: Timeout enabling PHY CLK0\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
set32(port_phy_base[port] + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK1REQ);
|
||||
if (poll32(port_phy_base[port] + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK1ACK,
|
||||
set32(state->port_phy_base[port] + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK1REQ);
|
||||
if (poll32(state->port_phy_base[port] + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK1ACK,
|
||||
APCIE_PHY_CTRL_CLK1ACK, 50000)) {
|
||||
printf("pcie: Timeout enabling PHY CLK1\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
clear32(port_phy_base[port] + APCIE_PHY_CTRL, 0x4000);
|
||||
set32(port_phy_base[port] + APCIE_PHY_CTRL, 0x200);
|
||||
set32(port_phy_base[port] + APCIE_PHY_CTRL, 0x400);
|
||||
clear32(state->port_phy_base[port] + APCIE_PHY_CTRL, 0x4000);
|
||||
set32(state->port_phy_base[port] + APCIE_PHY_CTRL, 0x200);
|
||||
set32(state->port_phy_base[port] + APCIE_PHY_CTRL, 0x400);
|
||||
|
||||
set32(port_base[port] + APCIE_T602X_PORT_RESET, APCIE_PORT_RESET_DIS);
|
||||
set32(state->port_base[port] + APCIE_T602X_PORT_RESET, APCIE_PORT_RESET_DIS);
|
||||
} else {
|
||||
/* PERSTN */
|
||||
set32(port_base[port] + APCIE_PORT_RESET, APCIE_PORT_RESET_DIS);
|
||||
set32(state->port_base[port] + APCIE_PORT_RESET, APCIE_PORT_RESET_DIS);
|
||||
}
|
||||
|
||||
if (poll32(port_base[port] + APCIE_PORT_STATUS, APCIE_PORT_STATUS_RUN,
|
||||
if (poll32(state->port_base[port] + APCIE_PORT_STATUS, APCIE_PORT_STATUS_RUN,
|
||||
APCIE_PORT_STATUS_RUN, 250000)) {
|
||||
printf("pcie: Port failed to come up on %s\n", bridge);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (poll32(port_base[port] + APCIE_PORT_LINKSTS, APCIE_PORT_LINKSTS_BUSY, 0, 250000)) {
|
||||
if (state->pcie_regs->type == APCIE_T602X && controller != APCIE) {
|
||||
write32(state->port_ltssm_base[port] + 0x10, 0x2);
|
||||
write32(state->port_ltssm_base[port] + 0x1c, 0x4);
|
||||
set32(state->port_ltssm_base[port] + 0x20, 0x2);
|
||||
write32(state->port_ltssm_base[port] + 0x14, 0x1);
|
||||
|
||||
clear32(state->port_base[port] + APCIE_PORT_APPCLK, 0x100);
|
||||
}
|
||||
|
||||
if (poll32(state->port_base[port] + APCIE_PORT_LINKSTS, APCIE_PORT_LINKSTS_BUSY, 0,
|
||||
250000)) {
|
||||
printf("pcie: Port failed to become idle on %s\n", bridge);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Do it again? */
|
||||
if (pcie_regs->type == APCIE_T602X) {
|
||||
clear32(port_base[port] + APCIE_T602X_PORT_RESET, APCIE_PORT_RESET_DIS);
|
||||
set32(port_base[port] + APCIE_T602X_PORT_RESET, APCIE_PORT_RESET_DIS);
|
||||
if (state->pcie_regs->type == APCIE_T602X && controller == APCIE) {
|
||||
clear32(state->port_base[port] + APCIE_T602X_PORT_RESET, APCIE_PORT_RESET_DIS);
|
||||
set32(state->port_base[port] + APCIE_T602X_PORT_RESET, APCIE_PORT_RESET_DIS);
|
||||
|
||||
if (poll32(port_base[port] + APCIE_PORT_LINKSTS, APCIE_PORT_LINKSTS_BUSY, 0, 250000)) {
|
||||
printf("pcie: Port failed to become idle on %s\n", bridge);
|
||||
if (poll32(state->port_base[port] + APCIE_PORT_LINKSTS, APCIE_PORT_LINKSTS_BUSY, 0,
|
||||
250000)) {
|
||||
printf("pcie: Port failed to become idle (2) on %s\n", bridge);
|
||||
return -1;
|
||||
}
|
||||
|
||||
udelay(1000);
|
||||
|
||||
write32(port_ltssm_base[port] + 0x10, 0x2);
|
||||
write32(port_ltssm_base[port] + 0x1c, 0x4);
|
||||
set32(port_ltssm_base[port] + 0x20, 0x2);
|
||||
write32(port_ltssm_base[port] + 0x14, 0x1);
|
||||
write32(state->port_ltssm_base[port] + 0x10, 0x2);
|
||||
write32(state->port_ltssm_base[port] + 0x1c, 0x4);
|
||||
set32(state->port_ltssm_base[port] + 0x20, 0x2);
|
||||
write32(state->port_ltssm_base[port] + 0x14, 0x1);
|
||||
}
|
||||
|
||||
/* Make Designware PCIe Core registers writable. */
|
||||
|
|
@ -577,54 +689,83 @@ int pcie_init(void)
|
|||
set32(config_base + DWC_DBI_LINK_WIDTH_SPEED_CONTROL, DWC_DBI_SPEED_CHANGE);
|
||||
}
|
||||
|
||||
/* Max link width 1 */
|
||||
/* Max link width */
|
||||
mask32(config_base + DWC_DBI_PORT_LINK_CONTROL, DWC_DBI_PORT_LINK_MODE,
|
||||
FIELD_PREP(DWC_DBI_PORT_LINK_MODE, DWC_DBI_PORT_LINK_MODE_1_LANE));
|
||||
FIELD_PREP(DWC_DBI_PORT_LINK_MODE, lane_mode));
|
||||
mask32(config_base + DWC_DBI_LINK_WIDTH_SPEED_CONTROL, DWC_DBI_LINK_WIDTH,
|
||||
FIELD_PREP(DWC_DBI_LINK_WIDTH, 1));
|
||||
FIELD_PREP(DWC_DBI_LINK_WIDTH, link_width));
|
||||
mask32(config_base + PCIE_CAP_BASE + PCIE_LNKCAP, PCIE_LNKCAP_MLW,
|
||||
FIELD_PREP(PCIE_LNKCAP_MLW, 1));
|
||||
FIELD_PREP(PCIE_LNKCAP_MLW, link_width));
|
||||
|
||||
/* Make Designware PCIe Core registers readonly. */
|
||||
clear32(config_base + DWC_DBI_RO_WR, DWC_DBI_RO_WR_EN);
|
||||
|
||||
if (pcie_regs->type == APCIE_T602X) {
|
||||
write32(port_base[port] + 0x4020, 0x3);
|
||||
write32(port_intr2axi_base[port] + 0x80, 0x1);
|
||||
if (state->pcie_regs->type == APCIE_T602X) {
|
||||
write32(state->port_base[port] + 0x4020, 0x3);
|
||||
if (state->port_intr2axi_base[port])
|
||||
write32(state->port_intr2axi_base[port] + 0x80, 0x1);
|
||||
|
||||
clear32(rc_base + 0x3c, 0x1);
|
||||
clear32(state->rc_base + 0x3c, 0x1);
|
||||
for (int i = 0; i < 32; i++)
|
||||
write32(port_base[port] + APCIE_T602X_PORT_MSIMAP + 4 * i, 0x80000000 | i);
|
||||
write32(state->port_base[port] + APCIE_T602X_PORT_MSIMAP + 4 * i, 0x80000000 | i);
|
||||
}
|
||||
|
||||
read32(port_base[port] + APCIE_PORT_LINKSTS);
|
||||
read32(state->port_base[port] + APCIE_PORT_LINKSTS);
|
||||
|
||||
/* Move to the next PCIe device on this bus. */
|
||||
config_base += (1 << 15);
|
||||
}
|
||||
|
||||
pcie_initialized = true;
|
||||
printf("pcie: Initialized.\n");
|
||||
printf("pcie: Initialized controller %d\n", controller);
|
||||
state->initialized = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int pcie_init(void)
|
||||
{
|
||||
bool success = false;
|
||||
|
||||
if (pcie_initialized)
|
||||
return 0;
|
||||
|
||||
success |= pcie_init_controller(APCIE, "/arm-io/apcie") == 0;
|
||||
success |= pcie_init_controller(APCIE_GE0, "/arm-io/apcie-ge0") == 0;
|
||||
success |= pcie_init_controller(APCIE_GE1, "/arm-io/apcie-ge1") == 0;
|
||||
|
||||
if (success)
|
||||
pcie_initialized = true;
|
||||
|
||||
return success ? 0 : -1;
|
||||
}
|
||||
|
||||
int pcie_shutdown(void)
|
||||
{
|
||||
if (!pcie_initialized)
|
||||
return 0;
|
||||
|
||||
for (u32 port = 0; port < port_count; port++) {
|
||||
if (pcie_regs->type == APCIE_T602X)
|
||||
clear32(port_base[port] + APCIE_T602X_PORT_RESET, APCIE_PORT_RESET_DIS);
|
||||
else
|
||||
clear32(port_base[port] + APCIE_PORT_RESET, APCIE_PORT_RESET_DIS);
|
||||
clear32(port_base[port] + APCIE_PORT_APPCLK, APCIE_PORT_APPCLK_EN);
|
||||
}
|
||||
for (u32 controller = 0; controller < NUM_CONTROLLERS; controller++) {
|
||||
struct state *state = &controllers[controller];
|
||||
|
||||
clear32(phy_base + APCIE_PHY_CTRL, APCIE_PHY_CTRL_RESET);
|
||||
clear32(phy_base + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK1REQ);
|
||||
clear32(phy_base + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK0REQ);
|
||||
if (!state->initialized)
|
||||
continue;
|
||||
|
||||
for (u32 port = 0; port < state->port_count; port++) {
|
||||
if (state->pcie_regs->type == APCIE_T602X)
|
||||
clear32(state->port_base[port] + APCIE_T602X_PORT_RESET, APCIE_PORT_RESET_DIS);
|
||||
else
|
||||
clear32(state->port_base[port] + APCIE_PORT_RESET, APCIE_PORT_RESET_DIS);
|
||||
clear32(state->port_base[port] + APCIE_PORT_APPCLK, APCIE_PORT_APPCLK_EN);
|
||||
}
|
||||
|
||||
for (int phy = 0; phy < state->num_phys; phy++) {
|
||||
clear32(state->phy_base[phy] + APCIE_PHY_CTRL, APCIE_PHY_CTRL_RESET);
|
||||
clear32(state->phy_base[phy] + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK1REQ);
|
||||
clear32(state->phy_base[phy] + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK0REQ);
|
||||
}
|
||||
|
||||
state->initialized = false;
|
||||
}
|
||||
|
||||
pcie_initialized = false;
|
||||
printf("pcie: Shutdown.\n");
|
||||
|
|
|
|||
Loading…
Reference in a new issue