mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-09-20 05:01:53 +00:00
aic: Add support for multi-die AIC2 as seen on the M1 Ultra
Multi-die IRQs are coded as in the ADT: die * max_irq + num Signed-off-by: Janne Grunau <j@jannau.net>
This commit is contained in:
Janne Grunau
Hector Martin
parent
524cb4a34f
commit
76fd226f7c
5 changed files with 154 additions and 73 deletions
137
src/aic.c
137
src/aic.c
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@ -6,49 +6,97 @@
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#include "assert.h"
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#include "utils.h"
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u64 aic_base;
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#define MASK_REG(x) (4 * ((x) >> 5))
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#define MASK_BIT(x) BIT((x)&GENMASK(4, 0))
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static const struct aic_regs aic1_regs = {
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.reg_size = AIC_REG_SIZE,
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.event = AIC_EVENT,
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.tgt_cpu = AIC_TARGET_CPU,
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.sw_set = AIC_SW_SET,
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.sw_clr = AIC_SW_CLR,
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.mask_set = AIC_MASK_SET,
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.mask_clr = AIC_MASK_CLR,
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static struct aic aic1 = {
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.version = 1,
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.nr_die = 1,
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.max_die = 1,
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.regs =
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{
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.reg_size = AIC_REG_SIZE,
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.event = AIC_EVENT,
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.tgt_cpu = AIC_TARGET_CPU,
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.sw_set = AIC_SW_SET,
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.sw_clr = AIC_SW_CLR,
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.mask_set = AIC_MASK_SET,
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.mask_clr = AIC_MASK_CLR,
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},
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};
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static const struct aic_regs aic2_regs = {
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.reg_size = AIC2_REG_SIZE,
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.event = AIC2_EVENT,
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.config = AIC2_IRQ_CFG,
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.sw_set = AIC2_SW_SET,
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.sw_clr = AIC2_SW_CLR,
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.mask_set = AIC2_MASK_SET,
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.mask_clr = AIC2_MASK_CLR,
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static struct aic aic2 = {
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.version = 2,
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.regs =
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{
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.config = AIC2_IRQ_CFG,
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},
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};
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const struct aic_regs *aic_regs;
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struct aic *aic;
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static void aic2_init(int node)
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static int aic2_init(int node)
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{
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int ret = ADT_GETPROP(adt, node, "aic-iack-offset", &aic->regs.event);
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if (ret < 0) {
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printf("AIC: failed to get property aic-iack-offset\n");
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return ret;
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}
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u32 info1 = read32(aic->base + AIC2_INFO1);
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aic->nr_die = FIELD_GET(AIC2_INFO1_LAST_DIE, info1) + 1;
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aic->nr_irq = FIELD_GET(AIC2_INFO1_NR_IRQ, info1);
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u32 info3 = read32(aic->base + AIC2_INFO3);
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aic->max_die = FIELD_GET(AIC2_INFO3_MAX_DIE, info3);
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aic->max_irq = FIELD_GET(AIC2_INFO3_MAX_IRQ, info3);
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if (aic->nr_die > AIC_MAX_DIES) {
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printf("AIC: more dies than supported: %u\n", aic->max_die);
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return -1;
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}
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if (aic->max_irq > AIC_MAX_HW_NUM) {
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printf("AIC: more IRQs than supported: %u\n", aic->max_irq);
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return -1;
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}
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const u64 start_off = aic->regs.config;
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u64 off = start_off + sizeof(u32) * aic->max_irq; /* IRQ_CFG */
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aic->regs.sw_set = off;
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off += sizeof(u32) * (aic->max_irq >> 5); /* SW_SET */
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aic->regs.sw_clr = off;
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off += sizeof(u32) * (aic->max_irq >> 5); /* SW_CLR */
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aic->regs.mask_set = off;
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off += sizeof(u32) * (aic->max_irq >> 5); /* MASK_SET */
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aic->regs.mask_clr = off;
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off += sizeof(u32) * (aic->max_irq >> 5); /* MASK_CLR */
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off += sizeof(u32) * (aic->max_irq >> 5); /* HW_STATE */
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aic->die_stride = off - start_off;
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aic->regs.reg_size = aic->regs.event + 4;
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printf("AIC: AIC2 with %u/%u dies, %u/%u IRQs, reg_size:%05lx die_stride:%05x\n", aic->nr_die,
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aic->max_die, aic->nr_irq, aic->max_irq, aic->regs.reg_size, aic->die_stride);
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u32 ext_intr_config_len;
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const u8 *ext_intr_config = adt_getprop(adt, node, "aic-ext-intr-cfg", &ext_intr_config_len);
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if (ext_intr_config) {
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printf("AIC: Configuring %d external interrupts\n", ext_intr_config_len / 3);
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for (u32 i = 0; i < ext_intr_config_len; i += 3) {
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u16 irq = ext_intr_config[i] | (ext_intr_config[i + 1] << 8);
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u8 die = ext_intr_config[i + 1] >> 4;
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u16 irq = ext_intr_config[i] | ((ext_intr_config[i + 1] & 0xf) << 8);
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u8 target = ext_intr_config[i + 2];
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assert(irq < 0x1000); // Will probably need updating for multi-die
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mask32(aic_base + aic_regs->config + 4 * irq, AIC2_IRQ_CFG_TARGET,
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FIELD_PREP(AIC2_IRQ_CFG_TARGET, target));
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assert(die < aic->nr_die);
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assert(irq < aic->nr_irq);
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mask32(aic->base + aic->regs.config + die * aic->die_stride + 4 * irq,
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AIC2_IRQ_CFG_TARGET, FIELD_PREP(AIC2_IRQ_CFG_TARGET, target));
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}
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}
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return;
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return 0;
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}
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void aic_init(void)
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@ -61,32 +109,45 @@ void aic_init(void)
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return;
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}
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if (adt_get_reg(adt, path, "reg", 0, &aic_base, NULL)) {
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if (adt_is_compatible(adt, node, "aic,1")) {
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aic = &aic1;
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} else if (adt_is_compatible(adt, node, "aic,2")) {
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aic = &aic2;
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} else {
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printf("AIC: Error: Unsupported version\n");
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return;
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}
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if (adt_get_reg(adt, path, "reg", 0, &aic->base, NULL)) {
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printf("Failed to get AIC reg property!\n");
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return;
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}
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if (adt_is_compatible(adt, node, "aic,1")) {
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printf("AIC: Version 1 @ 0x%lx\n", aic_base);
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aic_regs = &aic1_regs;
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} else if (adt_is_compatible(adt, node, "aic,2")) {
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printf("AIC: Version 2 @ 0x%lx\n", aic_base);
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aic_regs = &aic2_regs;
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aic2_init(node);
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} else {
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printf("AIC: Error: Unsupported version @ 0x%lx\n", aic_base);
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if (aic->version == 1) {
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printf("AIC: Version 1 @ 0x%lx\n", aic->base);
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aic->nr_irq = FIELD_GET(AIC_INFO_NR_HW, read32(aic->base + AIC_INFO));
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aic->max_irq = AIC1_MAX_IRQ;
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} else if (aic->version == 2) {
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printf("AIC: Version 2 @ 0x%lx\n", aic->base);
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int ret = aic2_init(node);
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if (ret < 0)
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aic = NULL;
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}
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}
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void aic_set_sw(int irq, bool active)
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{
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u32 die = irq / aic->max_irq;
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irq = irq % aic->max_irq;
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if (active)
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write32(aic_base + aic_regs->sw_set + MASK_REG(irq), MASK_BIT(irq));
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write32(aic->base + aic->regs.sw_set + die * aic->die_stride + MASK_REG(irq),
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MASK_BIT(irq));
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else
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write32(aic_base + aic_regs->sw_clr + MASK_REG(irq), MASK_BIT(irq));
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write32(aic->base + aic->regs.sw_clr + die * aic->die_stride + MASK_REG(irq),
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MASK_BIT(irq));
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}
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uint32_t aic_ack(void)
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{
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return read32(aic_base + aic_regs->event);
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return read32(aic->base + aic->regs.event);
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}
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17
src/aic.h
17
src/aic.h
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@ -5,7 +5,7 @@
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#include "types.h"
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extern u64 aic_base;
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#define AIC_MAX_DIES 4
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struct aic_regs {
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uint64_t reg_size;
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@ -18,7 +18,20 @@ struct aic_regs {
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uint64_t mask_clr;
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};
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extern const struct aic_regs *aic_regs;
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struct aic {
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uint64_t base;
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uint32_t version;
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uint32_t nr_irq;
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uint32_t nr_die;
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uint32_t max_irq;
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uint32_t max_die;
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uint32_t die_stride;
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struct aic_regs regs;
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};
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extern struct aic *aic;
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void aic_init(void);
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void aic_set_sw(int irq, bool active);
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@ -19,21 +19,24 @@
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#define AIC_CPU_IPI_MASK_SET(cpu) (0x5024 + ((cpu) << 7))
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#define AIC_CPU_IPI_MASK_CLR(cpu) (0x5028 + ((cpu) << 7))
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#define AIC2_REG_SIZE 0x10000
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#define AIC2_INFO 0x0004
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#define AIC2_LATENCY 0x0204
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#define AIC2_EVENT 0xc000
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#define AIC2_IRQ_CFG 0x2000
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#define AIC2_SW_SET 0x6000
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#define AIC2_SW_CLR 0x6200
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#define AIC2_MASK_SET 0x6400
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#define AIC2_MASK_CLR 0x6800
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#define AIC2_INFO1 0x0004
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#define AIC2_INFO2 0x0008
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#define AIC2_INFO3 0x000c
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#define AIC2_LATENCY 0x0204
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#define AIC2_IRQ_CFG 0x2000
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#define AIC2_IRQ_CFG_TARGET GENMASK(3, 0)
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#define AIC_INFO_NR_HW GENMASK(15, 0)
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#define AIC_EVENT_TYPE GENMASK(31, 16)
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#define AIC2_INFO1_NR_IRQ GENMASK(15, 0)
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#define AIC2_INFO1_LAST_DIE GENMASK(27, 24)
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#define AIC2_INFO3_MAX_IRQ GENMASK(15, 0)
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#define AIC2_INFO3_MAX_DIE GENMASK(27, 24)
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#define AIC_EVENT_DIE GENMASK(31, 24)
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#define AIC_EVENT_TYPE GENMASK(23, 16)
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#define AIC_EVENT_NUM GENMASK(15, 0)
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#define AIC_EVENT_TYPE_HW 1
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@ -46,4 +49,5 @@
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#define AIC_IPI_OTHER BIT(0)
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#define AIC_IPI_SELF BIT(31)
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#define AIC_MAX_HW_NUM (0x80 * 32)
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#define AIC1_MAX_IRQ 0x400
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#define AIC_MAX_HW_NUM (0x80 * 32) // max_irq of the M1 Max
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@ -2,6 +2,7 @@
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#include "exception.h"
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#include "aic.h"
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#include "aic_regs.h"
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#include "cpu_regs.h"
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#include "gxf.h"
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#include "iodev.h"
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@ -285,8 +286,9 @@ void exc_irq(u64 *regs)
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{
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u32 reason = aic_ack();
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printf("Exception: IRQ (from %s) type: %d num: %d mpidr: %lx\n", get_exception_source(0),
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reason >> 16, reason & 0xffff, mrs(MPIDR_EL1));
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printf("Exception: IRQ (from %s) die: %lu type: %lu num: %lu mpidr: %lx\n",
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get_exception_source(0), FIELD_GET(AIC_EVENT_DIE, reason),
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FIELD_GET(AIC_EVENT_TYPE, reason), FIELD_GET(AIC_EVENT_NUM, reason), mrs(MPIDR_EL1));
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UNUSED(regs);
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// print_regs(regs);
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41
src/hv_aic.c
41
src/hv_aic.c
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@ -9,14 +9,14 @@
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#define IRQTRACE_IRQ BIT(0)
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static u32 trace_hw_num[AIC_MAX_HW_NUM / 32];
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static u32 trace_hw_num[AIC_MAX_DIES][AIC_MAX_HW_NUM / 32];
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static void emit_irqtrace(u16 type, u16 num)
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static void emit_irqtrace(u16 die, u16 type, u16 num)
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{
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struct hv_evt_irqtrace evt = {
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.flags = IRQTRACE_IRQ,
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.type = type,
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.num = num,
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.num = die * aic->max_irq + num,
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};
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hv_wdt_suspend();
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@ -29,17 +29,21 @@ static bool trace_aic_event(struct exc_info *ctx, u64 addr, u64 *val, bool write
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if (!hv_pa_rw(ctx, addr, val, write, width))
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return false;
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if (addr != (aic_base + aic_regs->event) || write || width != 2) {
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if (addr != (aic->base + aic->regs.event) || write || width != 2) {
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return true;
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}
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u16 type = (*val & AIC_EVENT_TYPE) >> 16;
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u16 num = *val & AIC_EVENT_NUM;
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u16 die = FIELD_GET(AIC_EVENT_DIE, *val);
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u16 type = FIELD_GET(AIC_EVENT_TYPE, *val);
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u16 num = FIELD_GET(AIC_EVENT_NUM, *val);
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if (die > AIC_MAX_DIES)
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return true;
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switch (type) {
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case AIC_EVENT_TYPE_HW:
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if (trace_hw_num[num / 32] & BIT(num & 31)) {
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emit_irqtrace(type, num);
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if (trace_hw_num[die][num / 32] & BIT(num & 31)) {
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emit_irqtrace(die, type, num);
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}
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break;
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default:
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@ -54,17 +58,19 @@ bool hv_trace_irq(u32 type, u32 num, u32 count, u32 flags)
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{
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dprintf("HV: hv_trace_irq type: %u start: %u num: %u flags: 0x%x\n", type, num, count, flags);
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if (type == AIC_EVENT_TYPE_HW) {
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if (num >= AIC_MAX_HW_NUM || count > AIC_MAX_HW_NUM - num) {
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printf("HV: invalid IRQ range: (%u, %u)\n", num, num + count);
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u32 die = num / aic->max_irq;
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num %= AIC_MAX_HW_NUM;
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if (die >= aic->max_irq || num >= AIC_MAX_HW_NUM || count > AIC_MAX_HW_NUM - num) {
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printf("HV: invalid IRQ range: (%u, %u) for die %u\n", num, num + count, die);
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return false;
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}
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for (u32 n = num; n < num + count; n++) {
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switch (flags) {
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case IRQTRACE_IRQ:
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trace_hw_num[n / 32] |= BIT(n & 31);
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trace_hw_num[die][n / 32] |= BIT(n & 31);
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break;
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default:
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trace_hw_num[n / 32] &= ~(BIT(n & 31));
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trace_hw_num[die][n / 32] &= ~(BIT(n & 31));
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break;
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}
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}
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@ -73,20 +79,15 @@ bool hv_trace_irq(u32 type, u32 num, u32 count, u32 flags)
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return false;
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}
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if (!aic_base) {
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if (!aic) {
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printf("HV: AIC not initialized\n");
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return false;
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}
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static bool hooked = false;
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if (aic_base && !hooked) {
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u32 nr_hw = FIELD_GET(AIC_INFO_NR_HW, read32(aic_base + AIC_INFO));
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if (nr_hw > AIC_MAX_HW_NUM) {
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printf("HV: AIC supports more IRQs than expected! nr_hw: %u\n", nr_hw);
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return false;
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}
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hv_map_hook(aic_base, trace_aic_event, aic_regs->reg_size);
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if (aic && !hooked) {
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hv_map_hook(aic->base, trace_aic_event, aic->regs.reg_size);
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hooked = true;
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}
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