mirror of
https://github.com/AsahiLinux/m1n1
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m1n1/ane: Initial commit
Signed-off-by: Eileen Yoon <eyn@gmx.com>
This commit is contained in:
Eileen Yoon
Hector Martin
parent
a633b90634
commit
6ce14d8735
3 changed files with 437 additions and 0 deletions
43
proxyclient/experiments/ane.py
Executable file
43
proxyclient/experiments/ane.py
Executable file
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#!/usr/bin/env python3
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# SPDX-License-Identifier: MIT
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import sys, pathlib
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sys.path.append(str(pathlib.Path(__file__).resolve().parents[1]))
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from m1n1.setup import *
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from m1n1.shell import run_shell
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from m1n1.fw.ane import ANE
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import numpy as np
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from anect import anect_convert # pip install anect
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def f16encode(x): return np.float16(x).tobytes()
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def f16decode(b): return np.frombuffer(b[:2], dtype=np.float16)[0]
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ane = ANE(u)
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ane.power_up()
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if 1:
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rnges = [(0x26bc04000, 0x26bc28000, 'engine'),]
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mon = RegMonitor(u)
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for (start, end, name) in rnges:
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mon.add(start, end-start, name=name)
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mon.poll() # should work after ane.power_up()
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# curl -LJO https://www.dropbox.com/s/lpjap6w0kdlom1h/add.hwx?dl=0
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anec = anect_convert("add.hwx")
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req = ane.fw.setup(anec)
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x1 = f16encode(1.0)
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x2 = f16encode(2.0)
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ane.fw.send_src(req, x1, 0)
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ane.fw.send_src(req, x2, 1)
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ane.tm.enqueue_tq(req)
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ane.tm.execute_tq(req)
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x3 = ane.fw.read_dst(req, 0)
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print("what's 1+2? = %f" % f16decode(x3[:2]))
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run_shell(globals(), msg="Have fun!")
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197
proxyclient/m1n1/fw/ane.py
Normal file
197
proxyclient/m1n1/fw/ane.py
Normal file
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# SPDX-License-Identifier: MIT
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import struct
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from m1n1.hw.dart import DART
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from m1n1.hw.ane import ANERegs, ANEDARTRegs, ANETaskManager
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class ANE:
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PAGE_SIZE = 0x4000
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TILE_SIZE = 0x4000
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def __init__(self, u):
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self.u = u
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self.p = u.proxy
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self.name = "ane"
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self.p.pmgr_adt_clocks_enable(f'/arm-io/{self.name}')
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self.p.pmgr_adt_clocks_enable(f'/arm-io/dart-{self.name}')
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self.base_addr = u.adt[f'arm-io/{self.name}'].get_reg(0)[0]
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self.regs = ANERegs(self.u, self.base_addr)
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self.apply_static_tunables()
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ps_map = {
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"ane": 0x023b70c000,
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"ane0": 0x028e08c000,
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"ane1": 0x028e684000,
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"ane2": 0x228e08c000,
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"ane3": 0x228e684000,
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}
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self.ps_base_addr = ps_map[self.name]
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# we need a slight patch to dart
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self.dart = DART.from_adt(u, path=f'/arm-io/dart-{self.name}',
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instance=0, iova_range=(0x4000, 0xe0000000))
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self.dart.initialize()
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dart_regs = []
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for prop in range(3):
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dart_addr = self.u.adt[f'/arm-io/dart-{self.name}'].get_reg(prop)[0]
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dart_regs.append(ANEDARTRegs(self.u, dart_addr))
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self.dart_regs = dart_regs
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# hack to initialize base ttbr
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phys = self.u.memalign(self.PAGE_SIZE, self.PAGE_SIZE)
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self.dart.iomap_at(0, 0x0, phys, self.PAGE_SIZE)
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self.ttbr0_addr = self.dart.regs.TTBR[0, 0].val
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self.dart_regs[1].TTBR[0, 0].val = self.ttbr0_addr # DMA fails w/o
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self.dart_regs[2].TTBR[0, 0].val = self.ttbr0_addr # DMA fails w/o
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self.allocator = ANEAllocator(self)
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self.fw = ANEFirmware(self)
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self.tm = ANETaskManager(self)
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def apply_static_tunables(self): # this cost me a solid week
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static_tunables_map = [
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(0x0, 0x10), (0x38, 0x50020), (0x3c, 0xa0030),
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(0x400, 0x40010001), (0x600, 0x1ffffff),
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(0x738, 0x200020), (0x798, 0x100030),
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(0x7f8, 0x100000a), (0x900, 0x101), (0x410, 0x1100),
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(0x420, 0x1100), (0x430, 0x1100)]
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for (offset, value) in static_tunables_map:
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self.p.write32(self.base_addr + offset, value)
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def power_up(self):
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self.p.pmgr_adt_clocks_enable(f'/arm-io/{self.name}')
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self.p.pmgr_adt_clocks_enable(f'/arm-io/dart-{self.name}')
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self.power_down()
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for offset in range(0x0, 0x30+0x8, 0x8):
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self.p.write32(self.ps_base_addr + offset, 0xf)
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self.tm.reset()
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def power_down(self):
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for offset in reversed(range(0x0, 0x30+0x8, 0x8)):
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self.p.write32(self.ps_base_addr + offset, 0x300)
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def ioread(self, iova, size):
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return self.dart.ioread(0, iova & 0xffffffff, size)
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def iowrite(self, iova, buf):
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self.dart.iowrite(0, iova & 0xffffffff, buf)
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def round_up(self, x, y): return ((x+(y-1)) & (-y))
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class ANEBuffer:
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def __init__(self, mapid, phys, iova, size):
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self.mapid = mapid
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self.phys = phys
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self.iova = iova
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self.size = size
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class ANEAllocator:
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def __init__(self, ane):
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self.ane = ane
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self.mapid = 0
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self.map = {}
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def alloc_size(self, size):
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size = self.ane.round_up(size, self.ane.PAGE_SIZE)
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phys = self.ane.u.memalign(self.ane.PAGE_SIZE, size)
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self.ane.p.memset32(phys, 0, size)
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iova = self.ane.dart.iomap(0, phys, size)
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buf = ANEBuffer(self.mapid, phys, iova, size)
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self.map[self.mapid] = buf
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print("mapid %d: mapped phys 0x%x to iova 0x%06x for data w/ size 0x%06x"
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% (buf.mapid, buf.phys, buf.iova, buf.size))
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self.mapid += 1
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return buf.iova
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def alloc_data(self, data):
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iova = self.alloc_size(len(data))
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self.ane.iowrite(iova, data)
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return iova
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def dump_map(self):
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for mapid in self.map:
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buf = self.map[mapid]
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print('mapid %d: phys 0x%x, iova 0x%x, size 0x%x'
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% (buf.mapid, buf.phys, buf.iova, buf.size))
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class ANEEngineReq:
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def __init__(self, anec):
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self.anec = anec
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self.td_size = 0
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self.td_count = 0
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self.fifo_iova = 0
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self.nid = 0
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self.qid = 0
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self.bar = [0x0] * 0x20
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class ANEFirmware:
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FIFO_NID = 0x40
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FIFO_COUNT = 0x20
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FIFO_WIDTH = 0x400 # nextpow2(0x274)
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def __init__(self, ane):
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self.ane = ane
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def setup(self, anec):
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req = ANEEngineReq(anec)
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req.td_size = anec.td_size
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req.td_count = anec.td_count
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# setup immutable bar
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tsk_buf = anec.data[anec.tsk_start:anec.tsk_start+anec.tsk_size]
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req.bar[0] = self.ane.allocator.alloc_data(tsk_buf)
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krn_start = anec.tsk_start + self.ane.round_up(anec.tsk_size, 0x10)
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krn_buf = anec.data[krn_start:krn_start+anec.krn_size]
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req.bar[1] = self.ane.allocator.alloc_data(krn_buf)
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# setup mutable bar
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for bdx in range(0x20):
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if ((anec.tiles[bdx]) and (bdx >= 3)):
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size = anec.tiles[bdx] * self.ane.TILE_SIZE
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req.bar[bdx] = self.ane.allocator.alloc_size(size)
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self.make_fifo(req)
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return req
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def make_fifo(self, req):
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anec = req.anec
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pool_size = self.ane.round_up(self.FIFO_WIDTH * 2, self.ane.TILE_SIZE)
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fifo_iova = self.ane.allocator.alloc_size(pool_size)
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td_buf = anec.data[anec.tsk_start:anec.tsk_start+anec.td_size]
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fifo_head = self.set_nid(td_buf, self.FIFO_NID)
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fifo_tail = self.set_nid(td_buf, self.FIFO_NID + self.FIFO_COUNT)
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self.ane.iowrite(fifo_iova, fifo_head)
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self.ane.iowrite(fifo_iova + self.FIFO_WIDTH, fifo_tail)
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req.fifo_iova = fifo_iova
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req.nid = self.FIFO_NID
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req.qid = 4 # just the default queue
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def set_nid(self, td_buf, nid):
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hdr0 = struct.unpack('<L', td_buf[:4])[0]
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hdr0 = (hdr0 & 0xf00ffff) | ((nid & 0xff) << 16)
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return struct.pack('<L', hdr0) + td_buf[4:]
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def send_src(self, req, src_buf, idx):
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iova = req.bar[4 + req.anec.dst_count + idx]
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size = req.anec.src_sizes[idx]
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if (len(src_buf) < size):
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src_buf += b''*(size - len(src_buf))
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self.ane.iowrite(iova, src_buf[:size])
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def read_dst(self, req, idx):
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iova = req.bar[4 + idx]
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size = req.anec.dst_sizes[idx]
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return self.ane.ioread(iova, size)
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197
proxyclient/m1n1/hw/ane.py
Normal file
197
proxyclient/m1n1/hw/ane.py
Normal file
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# SPDX-License-Identifier: MIT
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from ..utils import *
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from .dart import DARTRegs
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import time
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class ANERegs(RegMap):
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PMGR1 = 0x738, Register32
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PMGR2 = 0x798, Register32
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PMGR3 = 0x7f8, Register32
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ASC_IO_RVBAR = 0x1050000, Register32
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ASC_EDPRCR = 0x1010310, Register32
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# 24hz clocks, counter at +4
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CLK0 = 0x1160008, Register32
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CTR0 = 0x116000c, Register32
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CLK1 = 0x1168008, Register32
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CTR1 = 0x116800c, Register32
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CLK2 = 0x1170000, Register32
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CTR2 = 0x1170004, Register32
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CLK3 = 0x1178000, Register32
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CTR3 = 0x1178004, Register32
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VERS = 0x1840000, Register32
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# for acks w/ rtkit
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GPIO0 = 0x1840048, Register32
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GPIO1 = 0x184004c, Register32
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GPIO2 = 0x1840050, Register32
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GPIO3 = 0x1840054, Register32
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GPIO4 = 0x1840058, Register32
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GPIO5 = 0x184005c, Register32
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GPIO6 = 0x1840060, Register32
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GPIO7 = 0x1840064, Register32
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class ANEDARTRegs(DARTRegs):
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UNK_CONFIG_68 = 0x68, Register32
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UNK_CONFIG_6c = 0x6c, Register32
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class R_TQINFO(Register32):
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UNK = 31, 16
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NID = 15, 0
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class TaskQueue(RegMap):
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STATUS = irange(0x00, 8, 0x148), Register32
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PRTY = irange(0x10, 8, 0x148), Register32
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FREE_SPACE = irange(0x14, 8, 0x148), Register32
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TQINFO = irange(0x1c, 8, 0x148), R_TQINFO
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BAR1 = (irange(0x20, 8, 0x148), irange(0x0, 0x20, 4)), Register32
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REQ_NID1 = irange(0xa0, 8, 0x148), Register32
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REQ_SIZE2 = irange(0xa4, 8, 0x148), Register32
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REQ_ADDR2 = irange(0xa8, 8, 0x148), Register32
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BAR2 = (irange(0xac, 8, 0x148), irange(0x0, 0x20, 4)), Register32
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REQ_NID2 = irange(0x12c, 8, 0x148), Register32
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REQ_SIZE1 = irange(0x130, 8, 0x148), Register32
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REQ_ADDR1 = irange(0x134, 8, 0x148), Register32
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class R_REQINFO(Register32):
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TDSIZE = 31, 16
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TDCOUNT = 15, 0
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class R_IRQINFO(Register32):
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CNT = 31, 24
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NID = 23, 16
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UNK1 = 15, 8
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UNK2 = 7, 0
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class TMRegs(RegMap):
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REQ_ADDR = 0x0, Register32
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REQ_INFO = 0x4, R_REQINFO
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REQ_PUSH = 0x8, Register32
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TQ_EN = 0xc, Register32
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IRQ_EVT1_CNT = 0x14, Register32
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IRQ_EVT1_DAT_INFO = 0x18, R_IRQINFO
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IRQ_EVT1_DAT_UNK1 = 0x1c, Register32
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IRQ_EVT1_DAT_TIME = 0x20, Register32
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IRQ_EVT1_DAT_UNK2 = 0x24, Register32
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IRQ_EVT2_CNT = 0x28, Register32
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IRQ_EVT2_DAT_INFO = 0x2c, R_IRQINFO
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IRQ_EVT2_DAT_UNK1 = 0x30, Register32
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IRQ_EVT2_DAT_TIME = 0x34, Register32
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IRQ_EVT2_DAT_UNK2 = 0x38, Register32
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COMMIT_INFO = 0x44, Register32
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TM_STATUS = 0x54, Register32
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UNK_IRQ_EN1 = 0x68, Register32
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UNK_IRQ_ACK = 0x6c, Register32
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UNK_IRQ_EN2 = 0x70, Register32
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class ANETaskManager:
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TQ_COUNT = 8
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TQ_WIDTH = 0x148
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tq_prty = (0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x1e, 0x1f)
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def __init__(self, ane):
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self.u = ane.u
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self.p = ane.p
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self.TM_BASE_ADDR = ane.base_addr + 0x1c00000 + 0x24000
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self.TQ_BASE_ADDR = ane.base_addr + 0x1c00000 + 0x25000
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self.regs = TMRegs(self.u, self.TM_BASE_ADDR)
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self.tq = TaskQueue(self.u, self.TQ_BASE_ADDR)
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def reset(self): # these reset with ANE_SET pds
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self.regs.TQ_EN.val = 0x3000
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# set priority param for each queue
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for qid, prty in enumerate(self.tq_prty):
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self.tq.PRTY[qid].val = self.tq_prty[qid]
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self.regs.UNK_IRQ_EN1.val = 0x4000000 # enable irq
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self.regs.UNK_IRQ_EN2.val = 0x6 # enable irq
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def enqueue_tq(self, req):
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qid = req.qid
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if not ((qid >= 1) and (qid < self.TQ_COUNT)):
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raise ValueError('1 <= qid <= 7')
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if not (self.tq.PRTY[qid].val == self.tq_prty[qid]):
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raise ValueError('invalid priority setup for tq %d' % qid)
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print('enqueueing task w/ fifo 0x%x to tq %d' % (req.fifo_iova, qid))
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self.tq.STATUS[qid].val = 0x1 # in use
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for bdx, iova in enumerate(req.bar):
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if (iova):
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print("bar %d: 0x%x" % (bdx, iova))
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self.tq.BAR1[qid, bdx].val = iova
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self.tq.REQ_SIZE1[qid].val = ((req.td_size << 0xe) + 0x1ff0000) & 0x1ff0000
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self.tq.REQ_ADDR1[qid].val = req.fifo_iova & 0xffffffff
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self.tq.REQ_NID1[qid].val = (req.nid & 0xff) << 8 | 1
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def execute_tq(self, req):
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qid = req.qid
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print('arbitered tq %d; pushing to execution queue...' % qid)
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# transfer to main queue (now in in TM range)
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self.regs.REQ_ADDR.val = self.tq.REQ_ADDR1[qid].val
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# doesnt go through if 0
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self.regs.REQ_INFO.val = self.tq.REQ_SIZE1[qid].val | req.td_count
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# let's do magic
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self.regs.REQ_PUSH.val = self.tq_prty[qid] | (qid & 7) << 8
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self.get_tm_status()
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self.get_committed_info()
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self.irq_handler()
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self.tq.STATUS[qid].val = 0x0 # done
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def get_tm_status(self, max_timeouts=100, interval=0.01):
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for n in range(max_timeouts):
|
||||
status = self.regs.TM_STATUS.val
|
||||
success = (status & 1) != 0
|
||||
print('tm status: 0x%x, success: %r' % (status, success))
|
||||
if (success):
|
||||
return success
|
||||
time.sleep(interval)
|
||||
print('timeout, tm is non-idle! status: 0x%x' % status)
|
||||
return success
|
||||
|
||||
def get_committed_info(self):
|
||||
committed_nid = self.regs.COMMIT_INFO.val >> 0x10 & 0xff
|
||||
print('pushed td w/ nid 0x%x to execution' % committed_nid)
|
||||
|
||||
def irq_handler(self):
|
||||
line = 0
|
||||
evtcnt = self.regs.IRQ_EVT1_CNT.val
|
||||
print('irq handler: LINE %d EVTCNT: %d' % (line, evtcnt))
|
||||
for evt_n in range(evtcnt): # needs to be cleared
|
||||
info = self.regs.IRQ_EVT1_DAT_INFO.val
|
||||
unk1 = self.regs.IRQ_EVT1_DAT_UNK1.val
|
||||
tmstmp = self.regs.IRQ_EVT1_DAT_TIME.val
|
||||
unk2 = self.regs.IRQ_EVT1_DAT_UNK2.val
|
||||
print('irq handler: LINE %d EVT %d: executed info 0x%x @ 0x%x'
|
||||
% (line, evt_n, info, tmstmp))
|
||||
|
||||
self.regs.UNK_IRQ_ACK.val = self.regs.UNK_IRQ_ACK.val | 2
|
||||
|
||||
line = 1
|
||||
evtcnt = self.regs.IRQ_EVT2_CNT.val
|
||||
print('irq handler: LINE %d EVTCNT: %d' % (line, evtcnt))
|
||||
for evt_n in range(evtcnt): # needs to be cleared
|
||||
info = self.regs.IRQ_EVT2_DAT_INFO.val
|
||||
unk1 = self.regs.IRQ_EVT2_DAT_UNK1.val
|
||||
tmstmp = self.regs.IRQ_EVT2_DAT_TIME.val
|
||||
unk2 = self.regs.IRQ_EVT2_DAT_UNK2.val
|
||||
print('irq handler: LINE %d EVT %d: executed info 0x%x @ 0x%x'
|
||||
% (line, evt_n, info, tmstmp))
|
||||
Loading…
Reference in a new issue