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https://github.com/AsahiLinux/m1n1
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aic_test: UART IRQ testing stuff
Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin
parent
63319ed348
commit
674a82a2bb
2 changed files with 221 additions and 13 deletions
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@ -1,5 +1,11 @@
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#!/usr/bin/python
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from setup import *
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import asm
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ULCON = 0x235200000
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UCON = 0x235200004
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UFCON = 0x235200008
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UTRSTAT = 0x235200010
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AIC = 0x23b100000
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AIC_TB = 0x23b108000
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@ -8,6 +14,7 @@ AIC_SW_GEN_SET = AIC + 0x4000
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AIC_SW_GEN_CLR = AIC + 0x4080
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AIC_MASK_SET = AIC + 0x4100
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AIC_MASK_CLR = AIC + 0x4180
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AIC_HW_STATE = AIC + 0x4200
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AIC_INTERRUPT_ACK = AIC + 0x2004
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AIC_IPI_SET = AIC + 0x2008
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@ -33,13 +40,14 @@ p.memset32(AIC_MASK_SET, 0xffffffff, 0x80)
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p.memset32(AIC_SW_GEN_CLR, 0xffffffff, 0x80)
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p.memset32(AIC_TGT_DST, 1, 0x1000)
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mon.add(AIC + 0x0000, 0x100)
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mon.add(AIC + 0x1000, 0x100)
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mon.add(AIC + 0x2008, 0x0f8)
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mon.add(AIC + 0x3000, 0x400)
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mon.add(AIC + 0x4000, 0x400)
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mon.add(AIC + 0x8000, 0x20)
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mon.add(AIC + 0x8030, 0xd0)
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#mon.add(AIC + 0x0000, 0x100)
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#mon.add(AIC + 0x1000, 0x100)
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#mon.add(AIC + 0x2008, 0x0f8)
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#mon.add(AIC + 0x3000, 0x400)
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#mon.add(AIC + 0x4000, 0x400)
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#mon.add(AIC + 0x8000, 0x20)
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#mon.add(AIC + 0x8030, 0xd0)
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mon.add(0x235200000, 0x20)
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def test_ipi():
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cpoll()
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@ -101,10 +109,195 @@ def test_timer():
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u.msr(CNTP_TVAL_EL0, freq * 2)
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u.msr(CNTP_CTL_EL0, 1)
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while True:
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p.nop()
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time.sleep(0.3)
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print(". %x" % u.mrs(CNTP_CTL_EL0))
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iface.ttymode()
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test_ipi()
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test_timer()
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#while True:
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#p.nop()
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#time.sleep(0.3)
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#print(". %x" % u.mrs(CNTP_CTL_EL0))
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def get_irq_state(irq):
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v = p.read32(AIC_HW_STATE + 4* (irq//32))
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return bool(v & 1<<(irq%32))
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def test_uart_irq():
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cpoll()
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#p.memset32(AIC_MASK_CLR, 0xffffffff, 0x80)
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print("cleanup")
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p.write32(UCON, 5)
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p.write32(UFCON, 0x11)
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p.write32(UTRSTAT, 0xfff)
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cpoll()
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for irq in range(600, 610):
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#print("S: ", get_irq_state(irq))
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p.write32(AIC_SW_GEN_CLR + 4* (irq//32), 1<<(irq%32))
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#print("S: ", get_irq_state(irq))
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#print("a")
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#print("S: ", get_irq_state(irq))
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p.write32(AIC_MASK_CLR + 4* (irq//32), 1<<(irq%32))
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#print("S: ", get_irq_state(irq))
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#print("b")
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irq = 605
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cpoll()
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print("a")
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print("S: ", get_irq_state(irq))
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print("ucon: %x" %p.read32(UCON))
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TX_IRQ_EN = 0x1000
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RX_IRQ_ENABLE = 0x20000
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RX_IRQ_UNMASK = 0x10000
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RX_IRQ_ENA = 0x20000
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RX_IRQ_MASK = 0x4000 # defer?
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code = u.malloc(0x1000)
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c = asm.ARMAsm("""
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ldr x1, =0x235200000
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ldr x3, =0xc000000
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1:
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subs x3, x3, #1
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bne 1b
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mov x2, 'A'
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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#str w2, [x1, #0x20]
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mov x3, #0x3ff
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str w3, [x1, #0x10]
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#str w2, [x1, #0x20]
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str w0, [x1, #4]
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ldr w0, [x1, #0x10]
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ldr x3, =0xc00000
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1:
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subs x3, x3, #1
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bne 1b
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#mov x3, #0x3ff
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#str w3, [x1, #0x10]
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#ldr w2, [x1, #4]
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#mov x2, #0x205
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#str w2, [x1, #4]
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#str w0, [x1, #4]
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##ldr w0, [x1, #0x10]
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#ldr x3, =0xc00000
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#1:
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#subs x3, x3, #1
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#bne 1b
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ldr w0, [x1, #0x10]
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#mov w0, w2
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ret
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""", code)
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iface.writemem(code, c.data)
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p.dc_cvau(code, len(c.data))
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p.ic_ivau(code, len(c.data))
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#RX_IRQ_
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"""
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UCON UTRSTAT
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00200 TX FIFO thresh IRQ delivery enable
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00080 0200 TX FIFO threshold IRQ unmask
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20000 0100 RX IRQ unmask
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10000 RX IRQ delivery enable
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"""
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# edge triggered
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TX_FIFO_THRESH_CROSSED_IRQ_UNMASK = 0x2000
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TX_IRQ_UNMASK = 0x200
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TX_EVENT_ENABLE = 0x80
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RX_EVENT_ENABLE = 0x20000
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RX_IRQ_UNMASK = 0x10000
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#flags = 0x7ffc0
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crash = 0x180000
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no_irqs = 0x21c5c0
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instant_irqs = 0x3a00
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#flags = no_irqs | 0x0000
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#flags = 0x2e5c0
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#flags = 0x2000
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#flags = 0x30000
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#flags = 0x80
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flags = 0x7ff80
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val = flags | 0x005
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#print("ucon<-%x" % val)
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#p.write32(UCON, val)
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p.write32(UTRSTAT, 0xfff)
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print("utrstat=%x" % p.read32(UTRSTAT))
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ret = p.call(code, val)
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print("utrstat::%x" % ret)
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print("utrstat=%x" % p.read32(UTRSTAT))
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time.sleep(0.5)
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iface.dev.write(b'1')
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#print(iface.dev.read(1))
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time.sleep(0.1)
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print("ucon: %x" %p.read32(UCON))
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print("delay")
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try:
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p.udelay(500000)
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except:
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pass
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iface.dev.write(bytes(64))
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p.nop()
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print("ucon: %x" %p.read32(UCON))
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print("S: ", get_irq_state(irq))
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#while True:
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#print("S: ", get_irq_state(irq))
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#p.write32(UTRSTAT, 0xfff)
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#print("utrstat=%x" % p.read32(UTRSTAT))
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#print("ucon: %x" %p.read32(UCON))
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#print(">S: ", get_irq_state(irq))
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#p.write32(UCON, flags | 0x005)
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#print(">ucon: %x" %p.read32(UCON))
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#time.sleep(0.1)
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#test_ipi()
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#test_timer()
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test_uart_irq()
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@ -52,12 +52,27 @@ void exc_sync(u64 *regs)
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void exc_irq(u64 *regs)
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{
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#ifdef DEBUG_UART_IRQS
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u32 ucon, utrstat, uerstat, ufstat;
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ucon = read32(0x235200004);
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utrstat = read32(0x235200010);
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uerstat = read32(0x235200014);
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ufstat = read32(0x235200018);
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#endif
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uart_puts("Exception: IRQ");
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u32 reason = read32(0x23b102004);
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printf(" type: %d num: %d\n", reason >> 16, reason & 0xffff);
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#ifdef DEBUG_UART_IRQS
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printf(" UCON: 0x%x\n", ucon);
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printf(" UTRSTAT: 0x%x\n", utrstat);
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printf(" UERSTAT: 0x%x\n", uerstat);
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printf(" UFSTAT: 0x%x\n", ufstat);
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#endif
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// print_regs(regs);
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}
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