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tools/gen_reg_class.py: Fix multibit field defs
Signed-off-by: Hector Martin <marcan@marcan.st>
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1 changed files with 1 additions and 1 deletions
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@ -28,6 +28,6 @@ for reg in data:
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if msb == lsb:
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if msb == lsb:
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print(f" {fname} = {lsb}")
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print(f" {fname} = {lsb}")
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else:
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else:
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print(f" {fname} {msb}, {lsb}")
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print(f" {fname} = {msb}, {lsb}")
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print()
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print()
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