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chickens: Add A7-A11 chickens

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Cyclone and Typhoon are similar enough to share a file.

Hurricane and Zephyr are the physical cores on A10 backing the
Hurricane-Zephyr logical core.

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
This commit is contained in:
Nick Chan 2024-08-25 15:15:17 +08:00 committed by Hector Martin
parent 5560190b36
commit 5dfb07f3da
8 changed files with 322 additions and 54 deletions
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4
Makefile
View file

@ -101,10 +101,14 @@ OBJECTS := \
chickens.o \ chickens.o \
chickens_avalanche.o \ chickens_avalanche.o \
chickens_blizzard.o \ chickens_blizzard.o \
chickens_cyclone_typhoon.o \
chickens_everest.o \ chickens_everest.o \
chickens_firestorm.o \ chickens_firestorm.o \
chickens_hurricane_zephyr.o \
chickens_monsoon_mistral.o \
chickens_icestorm.o \ chickens_icestorm.o \
chickens_sawtooth.o \ chickens_sawtooth.o \
chickens_twister.o \
clk.o \ clk.o \
cpufreq.o \ cpufreq.o \
dapf.o \ dapf.o \

141
src/chickens.c
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@ -6,29 +6,56 @@
#include "utils.h" #include "utils.h"
/* Part IDs in MIDR_EL1 */ /* Part IDs in MIDR_EL1 */
#define MIDR_PART_T8181_ICESTORM 0x20 #define MIDR_PART_S5L8960X_CYCLONE 0x1
#define MIDR_PART_T8181_FIRESTORM 0x21 #define MIDR_PART_T7000_TYPHOON 0x2
#define MIDR_PART_T8103_ICESTORM 0x22 #define MIDR_PART_T7001_TYPHOON 0x3
#define MIDR_PART_T8103_FIRESTORM 0x23 #define MIDR_PART_S8000_TWISTER 0x4
#define MIDR_PART_T6000_ICESTORM 0x24 #define MIDR_PART_S8001_3_TWISTER 0x5
#define MIDR_PART_T6000_FIRESTORM 0x25 #define MIDR_PART_T8010_2_HURRICANE 0x6
#define MIDR_PART_T6001_ICESTORM 0x28 #define MIDR_PART_T8011_HURRICANE 0x7
#define MIDR_PART_T6001_FIRESTORM 0x29 #define MIDR_PART_T8015_MONSOON 0x8
#define MIDR_PART_T8110_BLIZZARD 0x30 #define MIDR_PART_T8015_MISTRAL 0x9
#define MIDR_PART_T8110_AVALANCHE 0x31 #define MIDR_PART_T8020_VORTEX 0xb
#define MIDR_PART_T8112_BLIZZARD 0x32 #define MIDR_PART_T8020_TEMPSET 0xc
#define MIDR_PART_T8112_AVALANCHE 0x33 #define MIDR_PART_T8006_TEMPSET 0xf
#define MIDR_PART_T6020_BLIZZARD 0x34 #define MIDR_PART_T8027_VORTEX 0x10
#define MIDR_PART_T6020_AVALANCHE 0x35 #define MIDR_PART_T8027_TEMPSET 0x11
#define MIDR_PART_T6021_BLIZZARD 0x38 #define MIDR_PART_T8030_LIGHTNING 0x12
#define MIDR_PART_T6021_AVALANCHE 0x39 #define MIDR_PART_T8030_THUNDER 0x13
#define MIDR_PART_T6031_EVEREST 0x49 #define MIDR_PART_T8101_ICESTORM 0x20
#define MIDR_PART_T6031_SAWTOOTH 0x48 #define MIDR_PART_T8101_FIRESTORM 0x21
#define MIDR_PART_T8103_ICESTORM 0x22
#define MIDR_PART_T8103_FIRESTORM 0x23
#define MIDR_PART_T6000_ICESTORM 0x24
#define MIDR_PART_T6000_FIRESTORM 0x25
#define MIDR_PART_T8301_THUNDER 0x26
#define MIDR_PART_T6001_ICESTORM 0x28
#define MIDR_PART_T6001_FIRESTORM 0x29
#define MIDR_PART_T8110_BLIZZARD 0x30
#define MIDR_PART_T8110_AVALANCHE 0x31
#define MIDR_PART_T8112_BLIZZARD 0x32
#define MIDR_PART_T8112_AVALANCHE 0x33
#define MIDR_PART_T6020_BLIZZARD 0x34
#define MIDR_PART_T6020_AVALANCHE 0x35
#define MIDR_PART_T6021_BLIZZARD 0x38
#define MIDR_PART_T6021_AVALANCHE 0x39
#define MIDR_PART_T6031_EVEREST 0x49
#define MIDR_PART_T6031_SAWTOOTH 0x48
#define MIDR_REV_LOW GENMASK(3, 0) #define MIDR_REV_LOW GENMASK(3, 0)
#define MIDR_PART GENMASK(15, 4) #define MIDR_PART GENMASK(15, 4)
#define MIDR_REV_HIGH GENMASK(23, 20) #define MIDR_REV_HIGH GENMASK(23, 20)
void init_s5l8960x_cyclone(void);
void init_t7000_typhoon(void);
void init_t7001_typhoon(void);
void init_samsung_twister(int rev);
void init_tsmc_twister(void);
void init_t8010_2_hurricane_zephyr(void);
void init_t8011_hurricane_zephyr(void);
void init_t8015_monsoon(void);
void init_t8015_mistral(void);
void init_t8015_monsoon(void);
void init_m1_icestorm(void); void init_m1_icestorm(void);
void init_t8103_firestorm(int rev); void init_t8103_firestorm(int rev);
void init_t6000_firestorm(int rev); void init_t6000_firestorm(int rev);
@ -56,19 +83,66 @@ const char *init_cpu(void)
else else
reg_set(SYS_IMP_APL_HID4, HID4_DISABLE_DC_MVA | HID4_DISABLE_DC_SW_L2_OPS); reg_set(SYS_IMP_APL_HID4, HID4_DISABLE_DC_MVA | HID4_DISABLE_DC_SW_L2_OPS);
/* Enable NEX powergating, the reset cycles might be overriden by chickens */
if (!is_ecore()) {
reg_mask(SYS_IMP_APL_HID13, HID13_RESET_CYCLES_MASK, HID13_RESET_CYCLES(12));
reg_set(SYS_IMP_APL_HID14, HID14_ENABLE_NEX_POWER_GATING);
}
uint64_t midr = mrs(MIDR_EL1); uint64_t midr = mrs(MIDR_EL1);
int part = FIELD_GET(MIDR_PART, midr); int part = FIELD_GET(MIDR_PART, midr);
int rev = (FIELD_GET(MIDR_REV_HIGH, midr) << 4) | FIELD_GET(MIDR_REV_LOW, midr); int rev = (FIELD_GET(MIDR_REV_HIGH, midr) << 4) | FIELD_GET(MIDR_REV_LOW, midr);
printf(" CPU part: 0x%x rev: 0x%x\n", part, rev); printf(" CPU part: 0x%x rev: 0x%x\n", part, rev);
if (part >= MIDR_PART_T8015_MONSOON) {
/* Enable NEX powergating, the reset cycles might be overriden by chickens */
if (!is_ecore()) {
reg_mask(SYS_IMP_APL_HID13, HID13_RESET_CYCLES_MASK, HID13_RESET_CYCLES(12));
reg_set(SYS_IMP_APL_HID14, HID14_ENABLE_NEX_POWER_GATING);
}
}
switch (part) { switch (part) {
case MIDR_PART_S5L8960X_CYCLONE:
cpu = "A7 Cyclone";
init_s5l8960x_cyclone();
break;
case MIDR_PART_T7000_TYPHOON:
cpu = "A8 Typhoon";
init_t7000_typhoon();
break;
case MIDR_PART_T7001_TYPHOON:
cpu = "A8X Typhoon";
init_t7001_typhoon();
break;
case MIDR_PART_S8000_TWISTER:
cpu = "A9 Twister (Samsung)";
init_samsung_twister(rev);
break;
case MIDR_PART_S8001_3_TWISTER:
cpu = "A9(X) Twister (TSMC)";
init_tsmc_twister();
break;
case MIDR_PART_T8010_2_HURRICANE:
cpu = "A10/T2 Hurricane-Zephyr";
init_t8010_2_hurricane_zephyr();
break;
case MIDR_PART_T8011_HURRICANE:
cpu = "A10X Hurricane-Zephyr";
init_t8011_hurricane_zephyr();
break;
case MIDR_PART_T8015_MONSOON:
cpu = "A11 Monsoon";
init_t8015_monsoon();
break;
case MIDR_PART_T8015_MISTRAL:
cpu = "A11 Mistral";
init_t8015_mistral();
break;
case MIDR_PART_T8103_FIRESTORM: case MIDR_PART_T8103_FIRESTORM:
cpu = "M1 Firestorm"; cpu = "M1 Firestorm";
init_t8103_firestorm(rev); init_t8103_firestorm(rev);
@ -147,23 +221,26 @@ const char *init_cpu(void)
if (part >= MIDR_PART_T8110_BLIZZARD) if (part >= MIDR_PART_T8110_BLIZZARD)
cpufeat_actlr_el2 = true; cpufeat_actlr_el2 = true;
int core = mrs(MPIDR_EL1) & 0xff; if (part >= MIDR_PART_T8101_ICESTORM && part != MIDR_PART_T8301_THUNDER) {
int core = mrs(MPIDR_EL1) & 0xff;
msr(SYS_IMP_APL_AMX_CTX_EL1, core); // Enable IRQs (at least necessary on t600x)
msr(SYS_IMP_APL_AMX_CTL_EL1, 0x100); // XXX 0 causes pathological behavior in EL1, 2 works.
msr(SYS_IMP_APL_SIQ_CFG_EL1, 2);
sysop("isb");
// Enable IRQs (at least necessary on t600x) msr(SYS_IMP_APL_AMX_CTX_EL1, core);
// XXX 0 causes pathological behavior in EL1, 2 works. }
msr(SYS_IMP_APL_SIQ_CFG_EL1, 2);
sysop("isb"); if (part >= MIDR_PART_T8030_LIGHTNING)
msr(SYS_IMP_APL_AMX_CTL_EL1, 0x100);
/* Unmask external IRQs, set WFI mode to up (2) */ /* Unmask external IRQs, set WFI mode to up (2) */
reg_mask(SYS_IMP_APL_CYC_OVRD, reg_mask(SYS_IMP_APL_CYC_OVRD,
CYC_OVRD_FIQ_MODE_MASK | CYC_OVRD_IRQ_MODE_MASK | CYC_OVRD_WFI_MODE_MASK, CYC_OVRD_FIQ_MODE_MASK | CYC_OVRD_IRQ_MODE_MASK | CYC_OVRD_WFI_MODE_MASK,
CYC_OVRD_FIQ_MODE(0) | CYC_OVRD_IRQ_MODE(0) | CYC_OVRD_WFI_MODE(2)); CYC_OVRD_FIQ_MODE(0) | CYC_OVRD_IRQ_MODE(0) | CYC_OVRD_WFI_MODE(2));
/* Enable branch prediction state retention across ACC sleep */ // Enable branch prediction state retention across ACC sleep
reg_mask(SYS_IMP_APL_ACC_CFG, ACC_CFG_BP_SLEEP_MASK, ACC_CFG_BP_SLEEP(3)); reg_mask(SYS_IMP_APL_ACC_CFG, ACC_CFG_BP_SLEEP_MASK, ACC_CFG_BP_SLEEP(3));
return cpu; return cpu;

43
src/chickens_cyclone_typhoon.c Normal file
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@ -0,0 +1,43 @@
/* SPDX-License-Identifier: MIT */
#include "cpu_regs.h"
#include "utils.h"
// This file includes chickens for both cyclone and typhoon chips
// due to their similarity.
static void init_common_cyclone_typhoon(void)
{
/* "Disable LSP flush with context switch to work around bug in LSP
that can cause Cyclone to wedge when CONTEXTIDR is written." */
reg_set(SYS_IMP_APL_HID0, HID0_LOOP_BUFFER_DISABLE);
/* Not sure on what's happening here... did the meaning of this bit
change at some point? Original name: ARM64_REG_HID1_rccDisStallInactiveIexCtl */
reg_set(SYS_IMP_APL_HID1, HID1_DIS_SPEC_MDSB_INVL_ROB_FLUSH);
reg_set(SYS_IMP_APL_HID3, HID3_DIS_XMON_SNP_EVICT_TRIGGER_L2_STARAVTION_MODE);
reg_clr(SYS_IMP_APL_HID5, HID5_DIS_HWP_LD | HID5_DIS_HWP_ST);
// Change memcache data ID from 0 to 15
reg_set(SYS_IMP_APL_HID8, HID8_DATA_SET_ID0_VALUE(0xf) | HID8_DATA_SET_ID1_VALUE(0xf));
}
void init_t7000_typhoon(void)
{
init_common_cyclone_typhoon();
}
void init_t7001_typhoon(void)
{
init_common_cyclone_typhoon();
// Change memcache data ID from 0 to 15
reg_set(SYS_IMP_APL_HID8, HID8_DATA_SET_ID2_VALUE(0xf));
}
void init_s5l8960x_cyclone(void)
{
init_common_cyclone_typhoon();
reg_set(SYS_IMP_APL_HID1, HID1_DIS_LSP_FLUSH_WITH_CONTEXT_SWITCH);
}

39
src/chickens_hurricane_zephyr.c Normal file
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@ -0,0 +1,39 @@
/* SPDX-License-Identifier: MIT */
#include "cpu_regs.h"
#include "utils.h"
// This file name has both the codenames of E-core and P-core because to software
// it is one core that switches modes based on frequency
static void init_common_hurricane_zephyr(void)
{
/* "Increase Snoop reservation in EDB to reduce starvation risk
Needs to be done before MMU is enabled" */
reg_mask(SYS_IMP_APL_HID5, HID5_SNOOP_EDB_RESV_MASK, HID5_SNOOP_EDB_RESV_VALUE(2));
// "IC prefetch configuration"
reg_mask(SYS_IMP_APL_HID0, HID0_IC_PREFETCH_DEPTH_MASK, HID0_IC_PREFETCH_DEPTH_VALUE(1));
reg_set(SYS_IMP_APL_HID0, HID0_IC_PREFETCH_LIMIT_ONE_BRN);
// "disable reporting of TLB-multi-hit-error"
reg_clr(SYS_IMP_APL_LSU_ERR_CTL, LSU_ERR_CTL_DISABLE_TLB_MULTI_HIT_ERROR_REPORTING);
// "disable crypto fusion across decode groups"
/* Not sure on what's happening here... did the meaning of this bit
change at some point? Original Name: ARM64_REG_HID1_disAESFuseAcrossGrp */
reg_set(SYS_IMP_APL_HID1, HID1_CONSERVATIVE_SIQ);
}
void init_t8010_2_hurricane_zephyr(void)
{
init_common_hurricane_zephyr();
}
void init_t8011_hurricane_zephyr(void)
{
init_common_hurricane_zephyr();
reg_clr(SYS_IMP_APL_HID3, HID3_DISABLE_DC_ZVA_CMD_ONLY);
reg_clr(SYS_IMP_APL_EHID3, EHID3_DISABLE_DC_ZVA_CMD_ONLY);
}

27
src/chickens_monsoon_mistral.c Normal file
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@ -0,0 +1,27 @@
/* SPDX-License-Identifier: MIT */
#include "cpu_regs.h"
#include "utils.h"
static void init_t8015_common(void)
{
// "Disable refcount syncing between E and P"
reg_mask(SYS_IMP_APL_CYC_OVRD, CYC_OVRD_DSBL_SNOOP_TIME_MASK,
CYC_OVRD_DSBL_SNOOP_TIME_VALUE(2));
// "WKdm write ack lost when bif_wke_colorWrAck_XXaH asserts concurrently for both colors"
reg_set(SYS_IMP_APL_HID8, WKE_FORCE_STRICT_ORDER);
}
void init_t8015_mistral(void)
{
init_t8015_common();
// "Atomic launch eligibility is erroneously taken away when a store at SMB gets invalidated"
reg_clr(SYS_IMP_APL_EHID11, EHID11_SMB_DRAIN_THRESH_MASK);
}
void init_t8015_monsoon(void)
{
init_t8015_common();
}

33
src/chickens_twister.c Normal file
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@ -0,0 +1,33 @@
/* SPDX-License-Identifier: MIT */
#include "cpu_regs.h"
#include "utils.h"
static void init_twister_common(void)
{
reg_clr(SYS_IMP_APL_HID11_LEGACY, HID11_DISABLE_FILL_C1_BUB_OPT);
// Change memcache data ID from 0 to 15
reg_set(SYS_IMP_APL_HID8, HID8_DATA_SET_ID0_VALUE(0xf) | HID8_DATA_SET_ID1_VALUE(0xf) |
HID8_DATA_SET_ID2_VALUE(0xf) | HID8_DATA_SET_ID3_VALUE(0xf));
reg_set(SYS_IMP_APL_HID7, HID7_HID11_DISABLE_NEX_FAST_FMUL);
// "disable reporting of TLB-multi-hit-error"
reg_clr(SYS_IMP_APL_LSU_ERR_STS, LSU_ERR_STS_DISABLE_TLB_MULTI_HIT_ERROR_REPORTING);
}
void init_samsung_twister(int rev)
{
if (rev == 0x20) { // s8000 ONLY
/* "Set CYC_CFG:skipInit to pull in isAlive by one DCLK
to work around potential hang. Must only be applied to Maui C0." "*/
reg_set(SYS_IMP_APL_ACC_CFG, ACC_CFG_SKIP_INIT);
}
init_twister_common();
}
void init_tsmc_twister(void)
{
init_twister_common();
}

79
src/cpu_regs.h
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@ -22,9 +22,13 @@
/* HID registers */ /* HID registers */
#define SYS_IMP_APL_HID0 sys_reg(3, 0, 15, 0, 0) #define SYS_IMP_APL_HID0 sys_reg(3, 0, 15, 0, 0)
#define HID0_LOOP_BUFFER_DISABLE BIT(20)
#define HID0_IC_PREFETCH_LIMIT_ONE_BRN BIT(25)
#define HID0_FETCH_WIDTH_DISABLE BIT(28) #define HID0_FETCH_WIDTH_DISABLE BIT(28)
#define HID0_CACHE_FUSION_DISABLE BIT(36) #define HID0_CACHE_FUSION_DISABLE BIT(36)
#define HID0_SAME_PG_POWER_OPTIMIZATION BIT(45) #define HID0_SAME_PG_POWER_OPTIMIZATION BIT(45)
#define HID0_IC_PREFETCH_DEPTH_MASK GENMASK(62, 60)
#define HID0_IC_PREFETCH_DEPTH_VALUE(x) (ULONG(x) << 60)
#define SYS_IMP_APL_EHID0 sys_reg(3, 0, 15, 0, 1) #define SYS_IMP_APL_EHID0 sys_reg(3, 0, 15, 0, 1)
#define EHID0_BLI_UNK32 BIT(32) #define EHID0_BLI_UNK32 BIT(32)
@ -146,11 +150,13 @@
#define EHID1_EN_LFSR_STALL_RS6 BIT(62) #define EHID1_EN_LFSR_STALL_RS6 BIT(62)
#define EHID1_EN_LFSR BIT(63) #define EHID1_EN_LFSR BIT(63)
#define SYS_IMP_APL_HID3 sys_reg(3, 0, 15, 3, 0) #define SYS_IMP_APL_HID3 sys_reg(3, 0, 15, 3, 0)
#define HID3_DISABLE_ARBITER_FIX_BIF_CRD BIT(44) #define HID3_DISABLE_DC_ZVA_CMD_ONLY BIT(25)
#define HID3_DEV_PCIE_THROTTLE_LIMIT_MASK GENMASK(62, 57) #define HID3_DISABLE_ARBITER_FIX_BIF_CRD BIT(44)
#define HID3_DEV_PCIE_THROTTLE_LIMIT(x) ((ULONG(x)) << 57) #define HID3_DIS_XMON_SNP_EVICT_TRIGGER_L2_STARAVTION_MODE BIT(50)
#define HID3_DEV_PCIE_THROTTLE_ENABLE BIT(63) #define HID3_DEV_PCIE_THROTTLE_LIMIT_MASK GENMASK(62, 57)
#define HID3_DEV_PCIE_THROTTLE_LIMIT(x) ((ULONG(x)) << 57)
#define HID3_DEV_PCIE_THROTTLE_ENABLE BIT(63)
#define SYS_IMP_APL_HID4 sys_reg(3, 0, 15, 4, 0) #define SYS_IMP_APL_HID4 sys_reg(3, 0, 15, 4, 0)
#define HID4_INV_CORE_CLK_OBS_TO_SOC BIT(0) #define HID4_INV_CORE_CLK_OBS_TO_SOC BIT(0)
@ -209,6 +215,8 @@
#define HID4_ENABLE_LFSR BIT(63) #define HID4_ENABLE_LFSR BIT(63)
#define SYS_IMP_APL_EHID4 sys_reg(3, 0, 15, 4, 1) #define SYS_IMP_APL_EHID4 sys_reg(3, 0, 15, 4, 1)
#define SYS_IMP_APL_EHID3 sys_reg(3, 0, 15, 3, 1)
#define EHID3_DISABLE_DC_ZVA_CMD_ONLY BIT(25)
#define EHID4_DISABLE_HW_PREF_LD BIT(0) #define EHID4_DISABLE_HW_PREF_LD BIT(0)
#define EHID4_DISABLE_HW_PREF_ST BIT(1) #define EHID4_DISABLE_HW_PREF_ST BIT(1)
#define EHID4_DISABLE_SW_PRELOAD BIT(2) #define EHID4_DISABLE_SW_PRELOAD BIT(2)
@ -264,22 +272,38 @@
#define EHID4_LFSR_SEED_MASK GENMASK(62, 56) #define EHID4_LFSR_SEED_MASK GENMASK(62, 56)
#define EHID4_ENABLE_LFSR BIT(63) #define EHID4_ENABLE_LFSR BIT(63)
#define SYS_IMP_APL_HID5 sys_reg(3, 0, 15, 5, 0) #define SYS_IMP_APL_HID5 sys_reg(3, 0, 15, 5, 0)
#define HID5_BLZ_UNK_19_18_MASK GENMASK(19, 18) #define HID5_SNOOP_EDB_RESV_MASK GENMASK(15, 14)
#define HID5_BLZ_UNK18 BIT(18) #define HID5_SNOOP_EDB_RESV_VALUE(x) ((ULONG(x)) << 14)
#define HID5_BLZ_UNK19 BIT(19) #define HID5_BLZ_UNK_19_18_MASK GENMASK(19, 18)
#define HID5_DISABLE_FILL_2C_MERGE BIT(61) #define HID5_BLZ_UNK18 BIT(18)
#define HID5_BLZ_UNK19 BIT(19)
#define HID5_DIS_HWP_LD BIT(44)
#define HID5_DIS_HWP_ST BIT(45)
#define HID5_DISABLE_FILL_2C_MERGE BIT(61)
#define SYS_IMP_APL_HID6 sys_reg(3, 0, 15, 6, 0) #define SYS_IMP_APL_HID6 sys_reg(3, 0, 15, 6, 0)
#define HID6_UP_CRD_TKN_INIT_C2(x) ((ULONG(x)) << 5) #define HID6_UP_CRD_TKN_INIT_C2(x) ((ULONG(x)) << 5)
#define HID6_UP_CRD_TKN_INIT_C2_MASK (0x1FUL << 5) #define HID6_UP_CRD_TKN_INIT_C2_MASK (0x1FUL << 5)
#define SYS_IMP_APL_HID7 sys_reg(3, 0, 15, 7, 0) #define SYS_IMP_APL_HID7 sys_reg(3, 0, 15, 7, 0)
#define HID7_HID11_DISABLE_NEX_FAST_FMUL BIT(10)
#define HID7_FORCE_NONSPEC_IF_SPEC_FLUSH_POINTER_INVALID_AND_MP_VALID BIT(16) #define HID7_FORCE_NONSPEC_IF_SPEC_FLUSH_POINTER_INVALID_AND_MP_VALID BIT(16)
#define HID7_FORCE_NONSPEC_IF_STEPPING BIT(20) #define HID7_FORCE_NONSPEC_IF_STEPPING BIT(20)
#define HID7_FORCE_NONSPEC_TARGET_TIMER_SEL(x) ((ULONG(x)) << 24) #define HID7_FORCE_NONSPEC_TARGET_TIMER_SEL(x) ((ULONG(x)) << 24)
#define HID7_FORCE_NONSPEC_TARGET_TIMER_SEL_MASK (3UL << 24) #define HID7_FORCE_NONSPEC_TARGET_TIMER_SEL_MASK (3UL << 24)
#define SYS_IMP_APL_HID8 sys_reg(3, 0, 15, 8, 0)
#define HID8_DATA_SET_ID0_VALUE(x) ((ULONG(x)) << 4)
#define HID8_DATA_SET_ID0_VALUE_MASK GENMASK(7, 4)
#define HID8_DATA_SET_ID1_VALUE(x) ((ULONG(x)) << 8)
#define HID8_DATA_SET_ID1_VALUE_MASK GENMASK(11, 8)
#define WKE_FORCE_STRICT_ORDER BIT(35)
#define HID8_DATA_SET_ID2_VALUE(x) ((ULONG(x)) << 56)
#define HID8_DATA_SET_ID2_VALUE_MASK GENMASK(59, 56)
#define HID8_DATA_SET_ID3_VALUE(x) ((ULONG(x)) << 60)
#define HID8_DATA_SET_ID3_VALUE_MASK GENMASK(63, 60)
#define SYS_IMP_APL_HID9 sys_reg(3, 0, 15, 9, 0) #define SYS_IMP_APL_HID9 sys_reg(3, 0, 15, 9, 0)
#define HID9_AVL_UNK17 BIT(17) #define HID9_AVL_UNK17 BIT(17)
#define HID9_TSO_ALLOW_DC_ZVA_WC BIT(26) #define HID9_TSO_ALLOW_DC_ZVA_WC BIT(26)
@ -297,9 +321,14 @@
#define HID10_FORCE_WAIT_STATE_DRAIN_UC BIT(32) #define HID10_FORCE_WAIT_STATE_DRAIN_UC BIT(32)
#define HID10_DISABLE_ZVA_TEMPORAL_TSO BIT(49) #define HID10_DISABLE_ZVA_TEMPORAL_TSO BIT(49)
#define SYS_IMP_APL_HID11 sys_reg(3, 0, 15, 11, 0) #define SYS_IMP_APL_HID11 sys_reg(3, 0, 15, 11, 0)
#define HID11_ENABLE_FIX_UC_55719865 BIT(15) #define SYS_IMP_APL_HID11_LEGACY sys_reg(3, 0, 15, 13, 0) /* A7-A9 */
#define HID11_DISABLE_LD_NT_WIDGET BIT(59) #define HID11_DISABLE_FILL_C1_BUB_OPT BIT(7)
#define HID11_ENABLE_FIX_UC_55719865 BIT(15)
#define HID11_DISABLE_LD_NT_WIDGET BIT(59)
#define SYS_IMP_APL_EHID11 sys_reg(3, 0, 15, 11, 1)
#define EHID11_SMB_DRAIN_THRESH_MASK GENMASK(41, 40)
#define SYS_IMP_APL_HID12 sys_reg(3, 0, 15, 12, 0) #define SYS_IMP_APL_HID12 sys_reg(3, 0, 15, 12, 0)
@ -456,8 +485,12 @@
#define SYS_IMP_APL_PMC9 sys_reg(3, 2, 15, 10, 0) #define SYS_IMP_APL_PMC9 sys_reg(3, 2, 15, 10, 0)
#define SYS_IMP_APL_LSU_ERR_STS sys_reg(3, 3, 15, 0, 0) #define SYS_IMP_APL_LSU_ERR_STS sys_reg(3, 3, 15, 0, 0)
#define SYS_IMP_APL_LSU_ERR_CTL sys_reg(3, 3, 15, 1, 0)
#define SYS_IMP_APL_E_LSU_ERR_STS sys_reg(3, 3, 15, 2, 0) #define SYS_IMP_APL_E_LSU_ERR_STS sys_reg(3, 3, 15, 2, 0)
#define LSU_ERR_STS_DISABLE_TLB_MULTI_HIT_ERROR_REPORTING BIT(54)
#define LSU_ERR_CTL_DISABLE_TLB_MULTI_HIT_ERROR_REPORTING BIT(3)
#define SYS_IMP_APL_L2C_ERR_STS sys_reg(3, 3, 15, 8, 0) #define SYS_IMP_APL_L2C_ERR_STS sys_reg(3, 3, 15, 8, 0)
#define L2C_ERR_STS_RECURSIVE_FAULT BIT(1) #define L2C_ERR_STS_RECURSIVE_FAULT BIT(1)
@ -479,15 +512,19 @@
#define SYS_IMP_APL_ACC_CFG sys_reg(3, 5, 15, 4, 0) #define SYS_IMP_APL_ACC_CFG sys_reg(3, 5, 15, 4, 0)
#define ACC_CFG_BP_SLEEP(x) ((ULONG(x)) << 2) #define ACC_CFG_BP_SLEEP(x) ((ULONG(x)) << 2)
#define ACC_CFG_BP_SLEEP_MASK (3UL << 2) #define ACC_CFG_BP_SLEEP_MASK (3UL << 2)
#define ACC_CFG_DEEP_SLEEP BIT(24)
#define ACC_CFG_SKIP_INIT BIT(30)
#define SYS_IMP_APL_CYC_OVRD sys_reg(3, 5, 15, 5, 0) #define SYS_IMP_APL_CYC_OVRD sys_reg(3, 5, 15, 5, 0)
#define CYC_OVRD_FIQ_MODE(x) ((ULONG(x)) << 20) #define CYC_OVRD_FIQ_MODE(x) ((ULONG(x)) << 20)
#define CYC_OVRD_FIQ_MODE_MASK (3UL << 20) #define CYC_OVRD_FIQ_MODE_MASK (3UL << 20)
#define CYC_OVRD_IRQ_MODE(x) ((ULONG(x)) << 22) #define CYC_OVRD_IRQ_MODE(x) ((ULONG(x)) << 22)
#define CYC_OVRD_IRQ_MODE_MASK (3UL << 22) #define CYC_OVRD_IRQ_MODE_MASK (3UL << 22)
#define CYC_OVRD_WFI_MODE(x) ((ULONG(x)) << 24) #define CYC_OVRD_WFI_MODE(x) ((ULONG(x)) << 24)
#define CYC_OVRD_WFI_MODE_MASK (3UL << 24) #define CYC_OVRD_WFI_MODE_MASK (3UL << 24)
#define CYC_OVRD_DISABLE_WFI_RET BIT(0) #define CYC_OVRD_DISABLE_WFI_RET BIT(0)
#define CYC_OVRD_DSBL_SNOOP_TIME_MASK GENMASK(31, 30)
#define CYC_OVRD_DSBL_SNOOP_TIME_VALUE(x) (ULONG(x) << 30)
#define SYS_IMP_APL_ACC_OVRD sys_reg(3, 5, 15, 6, 0) #define SYS_IMP_APL_ACC_OVRD sys_reg(3, 5, 15, 6, 0)

10
src/utils.h
View file

@ -3,6 +3,7 @@
#ifndef UTILS_H #ifndef UTILS_H
#define UTILS_H #define UTILS_H
#include "soc.h"
#include "types.h" #include "types.h"
#define printf(...) debug_printf(__VA_ARGS__) #define printf(...) debug_printf(__VA_ARGS__)
@ -324,9 +325,16 @@ static inline void write64_lo_hi(u64 addr, u64 val)
#define dma_rmb() sysop("dmb oshld") #define dma_rmb() sysop("dmb oshld")
#define dma_wmb() sysop("dmb oshst") #define dma_wmb() sysop("dmb oshst")
extern u32 board_id, chip_id;
static inline bool has_ecores(void)
{
return !(chip_id == S5L8960X || chip_id == T7000 || chip_id == T7001 || chip_id == S8000 ||
chip_id == S8001 || chip_id == S8003);
}
static inline int is_ecore(void) static inline int is_ecore(void)
{ {
return !(mrs(MPIDR_EL1) & (1 << 16)); return has_ecores() && !(mrs(MPIDR_EL1) & (1 << 16));
} }
static inline int in_el2(void) static inline int in_el2(void)