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m1n1: hv: Use Apple implementation specific ACTLR_EL12 on M1*

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Fixes: 99571e5 ("hv: Use architectural ACTLR_EL12 on M2+")
Signed-off-by: Janne Grunau <j@jannau.net>
This commit is contained in:
Janne Grunau 2024-09-24 00:38:48 +02:00 committed by Hector Martin
parent b3e9eb1223
commit 5c8c3ccc7b
2 changed files with 14 additions and 2 deletions
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8
proxyclient/m1n1/hv/__init__.py
View file

@ -1441,9 +1441,13 @@ class HV(Reloadable):
self.map_vuart()
actlr = ACTLR(self.u.mrs(ACTLR_EL12))
# ACTLR depends on the CPU part
part = MIDR(self.u.mrs(MIDR_EL1)).PART
actlr_el12 = ACTLR_EL12 if part >= MIDR_PART.T8110_BLIZZARD else ACTLR_EL12_PRE
actlr = ACTLR(self.u.mrs(actlr_el12))
actlr.EnMDSB = 1
self.u.msr(ACTLR_EL12, actlr.value)
self.u.msr(actlr_el12, actlr.value)
self.setup_adt()

8
proxyclient/m1n1/sysreg.py
View file

@ -379,5 +379,13 @@ class TLBI_RVA(Register64):
TTL = 38, 37
BaseADDR = 36, 0
class MIDR_PART(IntEnum):
T8110_BLIZZARD = 0x30
class MIDR(Register64):
REV_LOW = 3, 0
PART = 15, 4
REV_HIGH = 23, 20
__all__.extend(k for k, v in globals().items()
if (callable(v) or isinstance(v, type)) and v.__module__ == __name__)