mirror of
https://github.com/AsahiLinux/m1n1
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cpu_regs,apple_regs.json: More registers
Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin
parent
234b7064ef
commit
59e0032ba4
5 changed files with 407 additions and 87 deletions
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@ -46,7 +46,7 @@ const char *init_cpu(void)
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/* This is performed unconditionally on all cores (necessary?) */
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if (is_ecore())
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reg_set(SYS_IMP_APL_EHID4, HID4_DISABLE_DC_MVA | HID4_DISABLE_DC_SW_L2_OPS);
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reg_set(SYS_IMP_APL_EHID4, EHID4_DISABLE_DC_MVA | EHID4_DISABLE_DC_SW_L2_OPS);
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else
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reg_set(SYS_IMP_APL_HID4, HID4_DISABLE_DC_MVA | HID4_DISABLE_DC_SW_L2_OPS);
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@ -136,7 +136,7 @@ const char *init_cpu(void)
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// Enable IRQs (at least necessary on t600x)
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// XXX 0 causes pathological behavior in EL1, 2 works.
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msr(s3_4_c15_c10_4, 2);
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msr(SYS_IMP_APL_SIQ_CFG_EL1, 2);
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sysop("isb");
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@ -37,4 +37,4 @@ void init_t6021_blizzard(void)
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reg_set(SYS_IMP_APL_EHID18, EHID18_BLZ_UNK34);
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reg_mask(SYS_IMP_APL_HID5, HID5_BLZ_UNK_19_18_MASK, HID5_BLZ_UNK19);
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}
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}
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@ -13,7 +13,7 @@ static void init_common_firestorm(void)
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reg_clr(SYS_IMP_APL_HID3, HID3_DEV_PCIE_THROTTLE_ENABLE | HID3_DISABLE_ARBITER_FIX_BIF_CRD);
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// "Post-silicon tuning of STNT widget contiguous counter threshold"
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reg_mask(SYS_IMP_APL_HID4, HID4_STNT_COUNTER_THRESHOLD_MASK, HID4_STNT_COUNTER_THRESHOLD(3));
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reg_mask(SYS_IMP_APL_HID4, HID4_CNF_CNTR_THRESH_MASK, HID4_CNF_CNTR_THRESH(3));
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// "Sibling Merge in LLC can cause UC load to violate ARM Memory Ordering Rules."
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reg_set(SYS_IMP_APL_HID5, HID5_DISABLE_FILL_2C_MERGE);
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@ -62,7 +62,7 @@ void init_t8103_firestorm(int rev)
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if (rev >= 0x10) {
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reg_set(SYS_IMP_APL_HID4,
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HID4_ENABLE_LFSR_STALL_LOAD_PIPE_2_ISSUE | HID4_ENABLE_LFSR_STALL_STQ_REPLAY);
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HID4_ENABLE_LFSR_STALL_LOAD_PIPE2_ISSUE | HID4_ENABLE_LFSR_STALL_STQ_REPLAY);
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reg_set(SYS_IMP_APL_HID9, HID9_FIX_BUG_55719865);
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reg_set(SYS_IMP_APL_HID11, HID11_ENABLE_FIX_UC_55719865);
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@ -86,7 +86,7 @@ void init_t6000_firestorm(int rev)
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reg_set(SYS_IMP_APL_HID1, HID1_ENABLE_MDSB_STALL_PIPELINE_ECO | HID1_ENABLE_BR_KILL_LIMIT);
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reg_set(SYS_IMP_APL_HID4,
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HID4_ENABLE_LFSR_STALL_LOAD_PIPE_2_ISSUE | HID4_ENABLE_LFSR_STALL_STQ_REPLAY);
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HID4_ENABLE_LFSR_STALL_LOAD_PIPE2_ISSUE | HID4_ENABLE_LFSR_STALL_STQ_REPLAY);
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reg_set(SYS_IMP_APL_HID18, HID18_SPAREBIT17);
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}
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@ -99,7 +99,7 @@ void init_t6001_firestorm(int rev)
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reg_set(SYS_IMP_APL_HID1, HID1_ENABLE_MDSB_STALL_PIPELINE_ECO);
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reg_set(SYS_IMP_APL_HID4,
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HID4_ENABLE_LFSR_STALL_LOAD_PIPE_2_ISSUE | HID4_ENABLE_LFSR_STALL_STQ_REPLAY);
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HID4_ENABLE_LFSR_STALL_LOAD_PIPE2_ISSUE | HID4_ENABLE_LFSR_STALL_STQ_REPLAY);
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reg_set(SYS_IMP_APL_HID9, HID9_FIX_BUG_55719865);
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367
src/cpu_regs.h
367
src/cpu_regs.h
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@ -27,15 +27,122 @@
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#define SYS_IMP_APL_EHID0 sys_reg(3, 0, 15, 0, 1)
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#define EHID0_BLI_UNK32 BIT(32)
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#define SYS_IMP_APL_HID1 sys_reg(3, 0, 15, 1, 0)
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#define HID1_TRAP_SMC BIT(54)
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#define HID1_ENABLE_MDSB_STALL_PIPELINE_ECO BIT(58)
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#define HID1_ENABLE_BR_KILL_LIMIT BIT(60)
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#define SYS_IMP_APL_HID1 sys_reg(3, 0, 15, 1, 0)
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#define HID1_RSS_FORCE_NS_ISSUE BIT(0)
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#define HID1_RSS_FORCE_NS_SPR_RD BIT(1)
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#define HID1_RSS_DIS_NS_STREAMING BIT(2)
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#define HID1_REDIR_FORCE_SPR_SYNC BIT(3)
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#define HID1_LSP_DISABLE BIT(4)
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#define HID1_FORCE_SSBS_ORDERING BIT(5)
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#define HID1_LSP_AGE_OUT_INTERVAL BIT(6)
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#define HID1_DIS_INT_ZCM BIT(8)
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#define HID1_DIS_NEON_ZCM BIT(9)
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#define HID1_FORCE_SPR_L3_CLK_ON BIT(10)
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#define HID1_DIS_MULT_RETIRE BIT(11)
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#define HID1_DIS_MULT_INDIR_BR_RETIRE BIT(12)
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#define HID1_DIS_BR_DISP_SYS_RSLVD_PTR BIT(13)
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#define HID1_DIS_CMP_BR_FUSION BIT(14)
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#define HID1_FORCE_NEX_L3_CLK_ON BIT(15)
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#define HID1_INTDISP_LIM_MODE BIT(16)
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#define HID1_NEON_DISP_LIM_MODE BIT(17)
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#define HID1_FORCE_PRECISE_NEON_GRP_MODE BIT(18)
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#define HID1_RCC_FORCE_ALL_MDR_L6_CLKS_ON BIT(19)
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#define HID1_RCC_FORCE_ALL_MDR_L3_CLKS_ON BIT(20)
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#define HID1_RCC_DIS_STALL_INACTIVE_MDR_CTL BIT(21)
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#define HID1_ZCL_RF_RESTART_THRESHOLD(x) ((ULONG(x)) << 22)
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#define HID1_ZCL_RF_RESTART_THRESHOLD_MASK GENMASK(23, 22)
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#define HID1_DIS_SPEC_MDSB_INVL_ROB_FLUSH BIT(24)
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#define HID1_DIS_LSP_FLUSH_WITH_CONTEXT_SWITCH BIT(25)
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#define HID1_DIS_WFE BIT(26)
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#define HID1_DIS_WFI BIT(27)
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#define HID1_EN_CS_RFOR_SP_SEL_IMM BIT(28)
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#define HID1_RCC_FORCE_CHKPT_L3_CLKS_ON BIT(29)
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#define HID1_DISABLE_CHKPT BIT(30)
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#define HID1_EN_SICILY_SDSB BIT(31)
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#define HID1_FORCE_WFE BIT(32)
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#define HID1_FORCE_GRP_BNDRY_ON_INST_END BIT(33)
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#define HID1_FORCE_GRP_BNDRY_ON_UCODE_END BIT(34)
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#define HID1_DIS_LCL_TIME_BASE BIT(35)
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#define HID1_EN_CS_RFOR_PAN_IMM BIT(36)
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#define HID1_EN_CS_RFOR_AMXT_IMM BIT(37)
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#define HID1_ZCL_SP_MISPREDICT_THRESHOLD(x) ((ULONG(x)) << 38)
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#define HID1_ZCL_SP_MISPREDICT_THRESHOLD_MASK GENMASK(39, 38)
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#define HID1_ZCL_SP_RESTART_THRESHOLD(x) ((ULONG(x)) << 40)
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#define HID1_ZCL_SP_RESTART_THRESHOLD_MASK GENMASK(41, 40)
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#define HID1_ZCL_RF_MISPREDICT_THRESHOLD(x) ((ULONG(x)) << 42)
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#define HID1_ZCL_RF_MISPREDICT_THRESHOLD_MASK GENMASK(43, 42)
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#define HID1_CONSERVATIVE_SIQ BIT(44)
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#define HID1_DIS_AES_FUSION BIT(45)
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#define HID1_RSS_DIS_MULTIPLE_CPM_IN_FLIGHT BIT(46)
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#define HID1_DIS_HW_TRACE_SYNC BIT(47)
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#define HID1_DIS_HW_TRACE_SYNC_ON_UARCH_REDIR BIT(48)
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#define HID1_DIS_MSR_SPEC_DAIF BIT(49)
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#define HID1_DIS_MRS_SPEC_DAIF BIT(50)
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#define HID1_DIS_MSR_SPEC_NON_DAIF BIT(51)
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#define HID1_DIS_MRS_SPEC_NON_DAIF BIT(52)
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#define HID1_DIS_DBG_PROG_OVRD BIT(53)
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#define HID1_TRAP_SMC BIT(54)
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#define HID1_ENABLE_MDSB_STALL_PIPELINE_ECO BIT(58)
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#define HID1_ENABLE_BR_KILL_LIMIT BIT(60)
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#define HID1_CPMU_DEBUG_OVF BIT(61)
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#define HID1_ZCL_RF_GNUM_DIST_MODE BIT(62)
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#define HID1_ZCL_RF_RESTART_THRESHOLD_MASK GENMASK(23, 22)
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#define HID1_ZCL_RF_RESTART_THRESHOLD(x) ((ULONG(x)) << 22)
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#define HID1_ZCL_RF_MISPREDICT_THRESHOLD_MASK GENMASK(43, 42)
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#define HID1_ZCL_RF_MISPREDICT_THRESHOLD(x) ((ULONG(x)) << 42)
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#define SYS_IMP_APL_EHID1 sys_reg(3, 0, 15, 1, 1)
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#define EHID1_RSS_FORCE_NS_ISSUE BIT(0)
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#define EHID1_RSS_FORCE_NS_SPR_RD BIT(1)
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#define EHID1_RSS_DIS_NS_STREAMING BIT(2)
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#define EHID1_REDIR_FORCE_SPR_SYNC BIT(3)
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#define EHID1_LSP_MODE(x) ((ULONG(X)) << 4)
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#define EHID1_LSP_MODE_MASK GENMASK(5, 4)
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#define EHID1_LSP_AGE_OUT_INTERVAL(x) ((ULONG(X)) << 6)
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#define EHID1_LSP_AGE_OUT_INTERVAL_MASK GENMASK(7, 6)
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#define EHID1_RSS_DIS_MULTIPLE_CPM_IN_FLIGHT BIT(8)
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#define EHID1_EN_CS_RFOR_AMXSETCLR BIT(9)
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#define EHID1_FORCE_SPR_L3_CLK_ON BIT(10)
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#define EHID1_DIS_MULT_RETIRE BIT(11)
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#define EHID1_DIS_MULT_INDIR_BR_RETIRE BIT(12)
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#define EHID1_DIS_BR_SYS_RSLV_PTR BIT(13)
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#define EHID1_DIS_CMP_BR_FUSION BIT(14)
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#define EHID1_FORCE_NEX_L3_CLK_ON BIT(15)
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#define EHID1_DIS_LCL_TIME_BASE BIT(16)
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#define EHID1_NEON_DISP_LIM_MODE BIT(17)
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#define EHID1_EN_CS_RFOR_PAN_IMM BIT(18)
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#define EHID1_RCC_FORCE_ALL_MDR_L6_CLKS_ON BIT(19)
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#define EHID1_RCC_FORCE_ALL_MDR_L3_CLKS_ON BIT(20)
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#define EHID1_RCC_DIS_STALL_INACTIVE_MDR_CTL BIT(21)
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#define EHID1_RCC_FORCE_ALL_IEX_L6_CLKS_ON BIT(22)
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#define EHID1_RCC_FORCE_ALL_IEX_L3_CLKS_ON BIT(23)
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#define EHID1_RCC_DIS_STALL_INACTIVE_IEX_CTL BIT(24)
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#define EHID1_DIS_LSP_FLUSH_WITH_CONTEXT_SWITCH BIT(25)
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#define EHID1_DIS_WFE BIT(26)
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#define EHID1_DIS_WFI BIT(27)
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#define EHID1_EN_CS_RFOR_SP_SEL_IMM BIT(28)
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#define EHID1_DIS_LSP_TRAIN_FILTER BIT(29)
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#define EHID1_DIS_MSR_SPEC_DAIF BIT(30)
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#define EHID1_DISABLE_CMP_BR_ACROSS_GRP BIT(31)
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#define EHID1_FORCE_WFE BIT(32)
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#define EHID1_FORCE_GRP_BNDRY_ON_INST_END BIT(33)
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#define EHID1_FORCE_GRP_BNDRY_ON_UCODE_END BIT(34)
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#define EHID1_LSP_CNT_INIT_VALUE(x) ((ULONG(X)) << 35)
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#define EHID1_LSP_CNT_INIT_VALUE_MASK GENMASK(37, 35)
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#define EHID1_LSP_CNT_RETRAIN_VALUE(x) ((ULONG(X)) << 38)
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#define EHID1_LSP_CNT_RETRAIN_VALUE_MASK GENMASK(40, 38)
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#define EHID1_LSP_CNT_INC_VALUE(x) ((ULONG(X)) << 41)
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#define EHID1_LSP_CNT_INC_VALUE_MASK GENMASK(43, 41)
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#define EHID1_LSP_CNT_RPLY_INIT_VALUE(x) ((ULONG(X)) << 44)
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#define EHID1_LSP_CNT_RPLY_INIT_VALUE_MASK GENMASK(46, 44)
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#define EHID1_DIS_MRS_SPEC_DAIF BIT(47)
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#define EHID1_PCSAMPLE_ALLRETIRES BIT(48)
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#define EHID1_DIS_AES_FUSION BIT(49)
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#define EHID1_DIS_ZCM BIT(50)
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#define EHID1_DIS_RETIRE_GREATER_THAN_TWO_GROUPS BIT(51)
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#define EHID1_LFSR_SEED(x) ((ULONG(X)) << 52)
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#define EHID1_LFSR_SEED_MASK GENMASK(58, 52)
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#define EHID1_EN_LFSR_STALL_RS01 BIT(59)
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#define EHID1_EN_LFSR_STALL_RS4 BIT(60)
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#define EHID1_CPMU_DEBUG_OVF BIT(61)
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#define EHID1_EN_LFSR_STALL_RS6 BIT(62)
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#define EHID1_EN_LFSR BIT(63)
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#define SYS_IMP_APL_HID3 sys_reg(3, 0, 15, 3, 0)
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#define HID3_DISABLE_ARBITER_FIX_BIF_CRD BIT(44)
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@ -43,14 +150,117 @@
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#define HID3_DEV_PCIE_THROTTLE_LIMIT(x) ((ULONG(x)) << 57)
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#define HID3_DEV_PCIE_THROTTLE_ENABLE BIT(63)
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#define SYS_IMP_APL_HID4 sys_reg(3, 0, 15, 4, 0)
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#define SYS_IMP_APL_EHID4 sys_reg(3, 0, 15, 4, 1)
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#define HID4_DISABLE_DC_MVA BIT(11)
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#define HID4_DISABLE_DC_SW_L2_OPS BIT(44)
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#define HID4_STNT_COUNTER_THRESHOLD(x) ((ULONG(x)) << 40)
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#define HID4_STNT_COUNTER_THRESHOLD_MASK (3UL << 40)
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#define HID4_ENABLE_LFSR_STALL_LOAD_PIPE_2_ISSUE BIT(49)
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#define HID4_ENABLE_LFSR_STALL_STQ_REPLAY BIT(53)
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#define SYS_IMP_APL_HID4 sys_reg(3, 0, 15, 4, 0)
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#define HID4_INV_CORE_CLK_OBS_TO_SOC BIT(0)
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#define HID4_DISABLE_STNT_WIDGET BIT(1)
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#define HID4_DISABLE_SW_PRELOAD BIT(2)
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#define HID4_DISABLE_ST_LD_REDIR_MULTI_HIT_CHK BIT(3)
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#define HID4_FORCE_CPU_OLDEST_IN_ORDER BIT(4)
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#define HID4_FORCE_S_STEP_STORE_COMMIT BIT(5)
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#define HID4_FORCE_S_STEP_PASS2_TO_CIF BIT(6)
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#define HID4_FORCE_ST_LNCH_NO_OLDER_LD BIT(7)
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#define HID4_DISABLE_LD_RTR_AHEAD_OLDER_ST BIT(8)
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#define HID4_DISABLE_SPEC_LS_REDIRECT BIT(9)
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#define HID4_DISABLE_SPEC_LDREX_PLAN_B BIT(0)
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#define HID4_DISABLE_DC_MVA BIT(11)
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#define HID4_ENABLE_CORE_CLK_OBS_TO_SOC BIT(12)
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#define HID4_RCC_FORCE_ALL_LSI_L6_CLKS_ON BIT(13)
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#define HID4_RCC_FORCE_ALL_LSU_L3_CLKS_ON BIT(14)
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#define HID4_RCC_DIS_STALL_INACTIVE_LSU_CTL BIT(15)
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#define HID4_DIS_ANTI_LIVELOCK_ON_LOCK_VICTIMIZATION BIT(16)
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#define HID4_CT0_ANTI_LIVELOCK_ON_LOCK_VICTIMIZATION(x) ((ULONG(x)) << 17)
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#define HID4_CT0_ANTI_LIVELOCK_ON_LOCK_VICTIMIZATION_MASK GENMASK(19, 17)
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#define HID4_CT1_ANTI_LIVELOCK_ON_LOCK_VICTIMIZATION(x) ((ULONG(x)) << 20)
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#define HID4_CT1_ANTI_LIVELOCK_ON_LOCK_VICTIMIZATION_MASK GENMASK(22, 20)
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#define HID4_CT2_ANTI_LIVELOCK_ON_LOCK_VICTIMIZATION(x) ((ULONG(x)) << 23)
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#define HID4_CT2_ANTI_LIVELOCK_ON_LOCK_VICTIMIZATION_MASK GENMASK(25, 23)
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#define HID4_CT0_ANTI_LIVELOCK_ON_OLDEST_LD_ST_REPLAY(x) ((ULONG(x)) << 26)
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#define HID4_CT0_ANTI_LIVELOCK_ON_OLDEST_LD_ST_REPLAY_MASK GENMASK(28, 26)
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#define HID4_CT0_ANTI_LIVELOCK_ON_LS_ISS_STALL_ON_LS_REPLAY(x) ((ULONG(x)) << 29)
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#define HID4_CT0_ANTI_LIVELOCK_ON_LS_ISS_STALL_ON_LS_REPLAY_MASK GENMASK(31, 29)
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#define HID4_DIS_ST_RTR_AHEAD_OLDER_LD BIT(32)
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#define HID4_DIS_SPEC_LNCH_READ BIT(33)
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#define HID4_FORCE_NS_ORD_LD_REQ_NO_OLDER_ST BIT(34)
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#define HID4_NON_CNTG_THRESH(x) ((ULONG(x)) << 35)
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#define HID4_NON_CNTG_THRESH_MASK GENMASK(36, 35)
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#define HID4_FORCE_YNG_LD_FLUSH_ON_BAR_OP BIT(37)
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#define HID4_FORCE_YNG_LD_FLUSH_ON_LD_ACQ BIT(38)
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#define HID4_FORCE_NS_ORD_LD_REQ_NO_OLDER_LD BIT(39)
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#define HID4_CNF_CNTR_THRESH(x) ((ULONG(x)) << 40)
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#define HID4_CNF_CNTR_THRESH_MASK GENMASK(41, 40)
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#define HID4_FORCE_BAR_LNCH_NO_OLDER_ST BIT(42)
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#define HID4_DISABLE_PWR_SAVE_LNBUF_CLK_OFF BIT(43)
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#define HID4_DISABLE_DC_SW_L2_OPS BIT(44)
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#define HID4_FORCE_NS_ORD_LD_REQ_NO_IN_PIPE_ORD_LD BIT(45)
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#define HID4_ENABLE_LFSR_STALL_STQ_RTR(x) ((ULONG(x)) << 46)
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#define HID4_ENABLE_LFSR_STALL_STQ_RTR_MASK GENMASK(47, 46)
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#define HID4_ENABLE_LFSR_STALL_LDQ_RTR BIT(48)
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#define HID4_ENABLE_LFSR_STALL_LOAD_PIPE2_ISSUE BIT(49)
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#define HID4_ENABLE_LFSR_STALL_PASS2_LAUNCH BIT(50)
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#define HID4_ENABLE_LFSR_STALL_LOAD_STORE_PIPE1_ISSUE BIT(51)
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#define HID4_ENABLE_LFSR_STALL_LOAD_STORE_PIPE0_ISSUE BIT(52)
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#define HID4_ENABLE_LFSR_STALL_STQ_REPLAY BIT(53)
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#define HID4_ENABLE_LFSR_STALL_LDQ_REPLAY BIT(54)
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#define HID4_ENABLE_LFSR_STALL_SMB_DRAIN BIT(55)
|
||||
#define HID4_LFSR_SEED(x) ((ULONG(x)) << 56)
|
||||
#define HID4_LFSR_SEED_MASK GENMASK(62, 56)
|
||||
#define HID4_ENABLE_LFSR BIT(63)
|
||||
|
||||
#define SYS_IMP_APL_EHID4 sys_reg(3, 0, 15, 4, 1)
|
||||
#define EHID4_DISABLE_HW_PREF_LD BIT(0)
|
||||
#define EHID4_DISABLE_HW_PREF_ST BIT(1)
|
||||
#define EHID4_DISABLE_SW_PRELOAD BIT(2)
|
||||
#define EHID4_DISABLE_ST_LD_REDIR_MULTI_HIT_CHK BIT(3)
|
||||
#define EHID4_FORCE_CPU_OLDEST_IN_ORDER BIT(4)
|
||||
#define EHID4_FORCE_S_STEP_STORE_COMMIT BIT(5)
|
||||
#define EHID4_FORCE_S_STEP_PASS2_TO_CIF BIT(6)
|
||||
#define EHID4_FORCE_ST_LNCH_NO_OLDER_LD BIT(7)
|
||||
#define EHID4_DISABLE_LD_RTR_AHEAD_OLDER_ST BIT(8)
|
||||
#define EHID4_DISABLE_SPEC_LS_REDIRECT BIT(9)
|
||||
#define EHID4_DISABLE_SPEC_LDREX_PLAN_B BIT(10)
|
||||
#define EHID4_DISABLE_DC_MVA BIT(11)
|
||||
#define EHID4_ENABLE_CORE_CLK_OBS_TO_SOC BIT(12)
|
||||
#define EHID4_RCC_FORCE_ALL_LSI_L6_CLKS_ON BIT(13)
|
||||
#define EHID4_RCC_FORCE_ALL_LSU_L3_CLKS_ON BIT(14)
|
||||
#define EHID4_RCC_DIS_STALL_INACTIVE_LSU_CTL BIT(15)
|
||||
#define EHID4_DISABLE_ANTI_LIVELOCK_ON_LOCK_VICTIMIZATION BIT(16)
|
||||
#define EHID4_CT0_ANTI_LIVELOCK_ON_LOCK_VICTIMIZATION(x) ((ULONG(x)) << 17)
|
||||
#define EHID4_CT0_ANTI_LIVELOCK_ON_LOCK_VICTIMIZATION_MASK GENMASK(19, 17)
|
||||
#define EHID4_CT1_ANTI_LIVELOCK_ON_LOCK_VICTIMIZATION(x) ((ULONG(x)) << 20)
|
||||
#define EHID4_CT1_ANTI_LIVELOCK_ON_LOCK_VICTIMIZATION_MASK GENMASK(22, 20)
|
||||
#define EHID4_CT2_ANTI_LIVELOCK_ON_LOCK_VICTIMIZATION(x) ((ULONG(x)) << 23)
|
||||
#define EHID4_CT2_ANTI_LIVELOCK_ON_LOCK_VICTIMIZATION_MASK GENMASK(25, 23)
|
||||
#define EHID4_CT0_ANTI_LIVELOCK_ON_OLDEST_LD_ST_REPLAY(x) ((ULONG(x)) << 26)
|
||||
#define EHID4_CT0_ANTI_LIVELOCK_ON_OLDEST_LD_ST_REPLAY_MASK GENMASK(28, 26)
|
||||
#define EHID4_CT0_ANTI_LIVELOCK_ON_LS_ISS_STALL_ON_LS_REPLAY(x) ((ULONG(x)) << 29)
|
||||
#define EHID4_CT0_ANTI_LIVELOCK_ON_LS_ISS_STALL_ON_LS_REPLAY_MASK GENMASK(31, 29)
|
||||
#define EHID4_DISABLE_HW_PREF_PG_CROSS BIT(32)
|
||||
#define EHID4_DISABLE_SPEC_LNCH_READ BIT(33)
|
||||
#define EHID4_FORCE_NS_ORD_LD_REQ_NO_OLDER_ST BIT(34)
|
||||
#define EHID4_RCC_FORCE_ALL_DC_DAT_L3_EN_ON BIT(35)
|
||||
#define EHID4_UNUSED_36 BIT(36)
|
||||
#define EHID4_FORCE_YNG_LD_FLUSH_ON_BAR_OP BIT(37)
|
||||
#define EHID4_FORCE_YNG_LD_FLUSH_ON_LD_ACQ BIT(38)
|
||||
#define EHID4_FORCE_NS_ORD_LD_REQ_NO_OLDER_LD BIT(39)
|
||||
#define EHID4_STNT_COUNTER_THRESHOLD(x) ((ULONG(x)) << 40)
|
||||
#define EHID4_STNT_COUNTER_THRESHOLD_MASK (3UL << 40)
|
||||
#define EHID4_DISABLE_HW_PREF_ZOMBIES BIT(40)
|
||||
#define EHID4_DISABLE_HW_PREF_ZOMBIES_LNCH_TO_CIF BIT(41)
|
||||
#define EHID4_FORCE_BAR_LNCH_NO_OLDER_ST BIT(42)
|
||||
#define EHID4_NON_ISA_FORCE_PROMOTE_WPT BIT(43)
|
||||
#define EHID4_DISABLE_DC_SW_L2_OPS BIT(44)
|
||||
#define EHID4_FORCE_NS_ORD_LD_REQ_NO_IN_PIPE_ORD_LD BIT(45)
|
||||
#define EHID4_ENABLE_LFSR_STALL_STQ_REPLAY BIT(48)
|
||||
#define EHID4_ENABLE_EN_LFSR_STALL_LDQ_REPLAY BIT(49)
|
||||
#define EHID4_ENABLE_LFSR_STALL_PASS2_LAUNCH BIT(50)
|
||||
#define EHID4_ENABLE_LFSR_STALL_LSRS1_ISSUE BIT(51)
|
||||
#define EHID4_ENABLE_LFSR_STALL_LSRS0_ISSUE BIT(52)
|
||||
#define EHID4_ENABLE_LFSR_STALL_STQ_RTR BIT(53)
|
||||
#define EHID4_ENABLE_LFSR_STALL_LDQ_RTR BIT(54)
|
||||
#define EHID4_ENABLE_LFSR_STALL_SMB_DRAIN BIT(55)
|
||||
#define EHID4_LFSR_SEED(x) (3UL << 56)
|
||||
#define EHID4_LFSR_SEED_MASK GENMASK(62, 56)
|
||||
#define EHID4_ENABLE_LFSR BIT(63)
|
||||
|
||||
#define SYS_IMP_APL_HID5 sys_reg(3, 0, 15, 5, 0)
|
||||
#define HID5_BLZ_UNK_19_18_MASK GENMASK(19, 18)
|
||||
|
|
@ -133,7 +343,58 @@
|
|||
#define SYS_IMP_APL_EHID18 sys_reg(3, 0, 15, 11, 3)
|
||||
#define EHID18_BLZ_UNK34 BIT(34)
|
||||
|
||||
#define SYS_IMP_APL_EHID20 sys_reg(3, 0, 15, 1, 2)
|
||||
#define SYS_IMP_APL_EHID20 sys_reg(3, 0, 15, 1, 2)
|
||||
#define EHID20_BLZ_DIS_HW_TRACE_SYNC_ON_UARCH_REDIR BIT(0)
|
||||
#define EHID20_BLZ_DIS_HW_TRACE_SYNC BIT(1)
|
||||
#define EHID20_BLZ_DIS_AMX_FUSION_ACROSS_GRP BIT(2)
|
||||
#define EHID20_BLZ_LSP_FORCE_SSBS_DEP BIT(3)
|
||||
#define EHID20_BLZ_FORCE_FP_SYNC_PRECISE_GRP_MODE BIT(4)
|
||||
#define EHID20_BLZ_DIS_DBG_PROG_OVRD BIT(5)
|
||||
#define EHID20_BLZ_CONSERVATIVE_SIQ BIT(6)
|
||||
#define EHID20_BLZ_FORCE_DMB_ON_ANY_TSO_ENTRY_EXIT BIT(7)
|
||||
#define EHID20_BLZ_DIS_SPEC_MDSB_INVL_ROB_FLUSH BIT(8)
|
||||
#define EHID20_BLZ_SPARE_9 BIT(9)
|
||||
#define EHID20_BLZ_DIS_MSR_SPEC_NON_DAIF BIT(10)
|
||||
#define EHID20_BLZ_DIS_MRS_SPEC_NON_DAIF BIT(11)
|
||||
#define EHID20_BLZ_FORCE_IEX_DISP_BIAS_MODE2 BIT(12)
|
||||
#define EHID20_BLZ_FORCE_NON_SPEC_IF_SPEC_FLUSH_PTR_INVALID_AND_MP_VALID BIT(13)
|
||||
#define EHID20_BLZ_DIS_SPEC_MDSB_UNTRUSTED_INVL_ROB_FLUSH BIT(14)
|
||||
#define EHID20_BLZ_FORCE_NON_SPEC_IF_NEXT_ROB_FLUSH_DISABLED BIT(15)
|
||||
#define EHID20_BLZ_FORCE_NON_SPEC_IF_OLDEST_REDIR_VLD_AND_OLDER BIT(16)
|
||||
#define EHID20_BLZ_FORCE_NON_SPEC_IF_SPEC_FLUSH_PTR_NE_BLK_RTR_PTR BIT(17)
|
||||
#define EHID20_BLZ_FORCE_NON_SPEC_IF_STEPPING BIT(18)
|
||||
#define EHID20_BLZ_FORCE_NON_SPEC_TIMER BIT(19)
|
||||
#define EHID20_BLZ_FORCE_NON_SPEC_TIMER_SEL(x) ((ULONG(x)) << 20)
|
||||
#define EHID20_BLZ_FORCE_NON_SPEC_TIMER_SEL_MASK GENMASK(21, 20)
|
||||
#define EHID20_BLZ_FORCE_NON_SPEC_TARGETED_TIMER_SEL(x) ((ULONG(x)) << 22)
|
||||
#define EHID20_BLZ_FORCE_NON_SPEC_TARGETED_TIMER_SEL_MASK GENMASK(23, 22)
|
||||
#define EHID20_BLZ_DIS_LD_CBZ_TBZ_FUSION BIT(24)
|
||||
#define EHID20_BLZ_DIS_CMP_CSEL_FUSION BIT(25)
|
||||
#define EHID20_BLZ_DIS_MULT_BR_RETIRE BIT(26)
|
||||
#define EHID20_BLZ_DIS_INT_FV_ODD_BANKS BIT(27)
|
||||
#define EHID20_BLZ_DIS_NEON_FV_ODD_BANKS BIT(28)
|
||||
#define EHID20_BLZ_MIN_REWIND_STALL(x) ((ULONG(x)) << 29)
|
||||
#define EHID20_BLZ_MIN_REWIND_STALL_MASK GENMASK(30, 29)
|
||||
#define EHID20_BLZ_SPARE_31 BIT(31)
|
||||
#define EHID20_BLZ_SPARE_32 BIT(32)
|
||||
#define EHID20_BLZ_SPARE_33 BIT(33)
|
||||
#define EHID20_BLZ_SPARE_34 BIT(34)
|
||||
#define EHID20_BLZ_SIQ_USE_MDR_BR_SYS_RSLV BIT(35)
|
||||
#define EHID20_BLZ_M_DSB_RESTART_IF_OLDER_REDIR BIT(36)
|
||||
#define EHID20_BLZ_ALWAYS_INCLUSIVE_EFAR_FLUSH BIT(37)
|
||||
#define EHID20_BLZ_UNTRUSTED_SNAPSHOT BIT(38)
|
||||
#define EHID20_BLZ_SPEC_MDSB_ASYNC_EXIT_STALL_FIX_DISABLE BIT(39)
|
||||
#define EHID20_BLZ_DIS_ITLB_PREF_FILL BIT(53)
|
||||
#define EHID20_BLZ_DIS_DMD_MERGE_PREF_FILL_FWD BIT(54)
|
||||
#define EHID20_BLZ_DISABLE_PWR_OPT BIT(55)
|
||||
#define EHID20_BLZ_INC_MISS_Q_WATER_MARK(x) ((ULONG(x)) << 56)
|
||||
#define EHID20_BLZ_INC_MISS_Q_WATER_MARK_MASK GENMASK(59, 56)
|
||||
#define EHID20_BLZ_DISABLE_IC_MISS_PERF_OPT BIT(60)
|
||||
#define EHID20_BLZ_DISABLE_ITLB_PREFETCH BIT(61)
|
||||
#define EHID20_BLZ_ENABLE_IC_TAG_CFM_PWR_OPT_ON_PAGE_BNDRY BIT(62)
|
||||
#define EHID20_BLZ_DISABLE_IC_TAG_CFM_PWR_OPT BIT(63)
|
||||
|
||||
// Older cores, off by 1?
|
||||
#define EHID20_TRAP_SMC BIT(8)
|
||||
#define EHID20_FORCE_NONSPEC_IF_OLDEST_REDIR_VALID_AND_OLDER BIT(15)
|
||||
#define EHID20_FORCE_NONSPEC_IF_SPEC_FLUSH_POINTER_NE_BLK_RTR_POINTER BIT(16)
|
||||
|
|
@ -204,6 +465,8 @@
|
|||
#define SYS_IMP_APL_FED_ERR_STS sys_reg(3, 4, 15, 0, 0)
|
||||
#define SYS_IMP_APL_E_FED_ERR_STS sys_reg(3, 4, 15, 0, 2)
|
||||
|
||||
#define SYS_IMP_APL_SIQ_CFG_EL1 sys_reg(3, 4, 15, 10, 4)
|
||||
|
||||
#define SYS_IMP_APL_MMU_ERR_STS sys_reg(3, 6, 15, 0, 0)
|
||||
#define SYS_IMP_APL_E_MMU_ERR_STS sys_reg(3, 6, 15, 2, 0)
|
||||
|
||||
|
|
@ -223,19 +486,63 @@
|
|||
|
||||
#define SYS_IMP_APL_ACC_OVRD sys_reg(3, 5, 15, 6, 0)
|
||||
|
||||
#define ACC_OVRD_PWR_DN_SRM(x) ((ULONG(x)) << 13)
|
||||
#define ACC_OVRD_PWR_DN_SRM_MASK GENMASK(14, 13)
|
||||
#define ACC_OVRD_DIS_L2_FLUSH_ACC_SLEEP(x) ((ULONG(x)) << 15)
|
||||
#define ACC_OVRD_DIS_L2_FLUSH_ACC_SLEEP_MASK GENMASK(16, 15)
|
||||
#define ACC_OVRD_TRAIN_DOWN_LINK(x) ((ULONG(x)) << 17)
|
||||
#define ACC_OVRD_TRAIN_DOWN_LINK_MASK GENMASK(18, 17)
|
||||
#define ACC_OVRD_POWER_DOWN_CPM(x) ((ULONG(x)) << 25)
|
||||
#define ACC_OVRD_POWER_DOWN_CPM_MASK GENMASK(26, 25)
|
||||
#define ACC_OVRD_CPM_WAKE_UP(x) ((ULONG(x)) << 27)
|
||||
#define ACC_OVRD_CPM_WAKE_UP_MASK GENMASK(28, 27)
|
||||
#define ACC_OVRD_DISABLE_CLK_DTR BIT(29)
|
||||
#define ACC_OVRD_DISABLE_PIO_ON_WFI_CPU BIT(32)
|
||||
#define ACC_OVRD_DEEP_SLEEP BIT(34)
|
||||
#define ACC_OVRD_PRE_RESET_CLK_CNTS (ULONG(x))
|
||||
#define ACC_OVRD_PRE_RESET_CLK_CNTS_MASK GENMASK(3, 0)
|
||||
#define ACC_OVRD_FRC_PSM_COND_L3_D_ON BIT(4)
|
||||
#define ACC_OVRD_SSB_DIVS_UPD_REQ (ULONG(x << 5))
|
||||
#define ACC_OVRD_SSB_DIVS_UPD_REQ_MASK GENMASK(6, 5)
|
||||
#define ACC_OVRD_SSB_DIVS_SEL (ULONG(x << 7))
|
||||
#define ACC_OVRD_SSB_DIVS_SEL_MASK GENMASK(8, 7)
|
||||
#define ACC_OVRD_DOM_CAN_BE_ON_IN_REF_CLK BIT(9)
|
||||
#define ACC_OVRD_HALT_LLC_BFR_RUN BIT(10)
|
||||
#define ACC_OVRD_DIS_TB_PUSH BIT(11)
|
||||
#define ACC_OVRD_MISR_EN BIT(12)
|
||||
#define ACC_OVRD_PWR_DN_SRM(x) ((ULONG(x)) << 13)
|
||||
#define ACC_OVRD_PWR_DN_SRM_MASK GENMASK(14, 13)
|
||||
#define ACC_OVRD_DIS_L2_FLUSH_ACC_SLEEP(x) ((ULONG(x)) << 15)
|
||||
#define ACC_OVRD_DIS_L2_FLUSH_ACC_SLEEP_MASK GENMASK(16, 15)
|
||||
#define ACC_OVRD_TRAIN_DOWN_LINK(x) ((ULONG(x)) << 17)
|
||||
#define ACC_OVRD_TRAIN_DOWN_LINK_MASK GENMASK(18, 17)
|
||||
#define ACC_OVRD_DVFM_SAFE_VOL BIT(19)
|
||||
#define ACC_OVRD_FRC_ZOUT_AMX_PWR_DN_TMR BIT(20)
|
||||
#define ACC_OVRD_RC_ACK_INTR_LOCK BIT(21)
|
||||
#define ACC_OVRD_CONVERT_SIQ_TO_IRQ BIT(22)
|
||||
#define ACC_OVRD_VOL_UPD_ACK(x) ((ULONG(x)) << 23)
|
||||
#define ACC_OVRD_VOL_UPD_ACK_MASK GENMASK(24, 23)
|
||||
#define ACC_OVRD_POWER_DOWN_CPM(x) ((ULONG(x)) << 25)
|
||||
#define ACC_OVRD_POWER_DOWN_CPM_MASK GENMASK(26, 25)
|
||||
#define ACC_OVRD_CPM_WAKE_UP(x) ((ULONG(x)) << 27)
|
||||
#define ACC_OVRD_CPM_WAKE_UP_MASK GENMASK(28, 27)
|
||||
#define ACC_OVRD_DISABLE_CLK_DTR BIT(29)
|
||||
#define ACC_OVRD_DISABLE_PSW_OFF_ABORT BIT(30)
|
||||
#define ACC_OVRD_RESET_CPM BIT(31)
|
||||
#define ACC_OVRD_DISABLE_PIO_ON_WFI_CPU BIT(32)
|
||||
#define ACC_OVRD_DEEP_SLEEP BIT(34)
|
||||
#define ACC_OVRD_C2_WAKE_UP BIT(35)
|
||||
#define ACC_OVRD_BYPASS_LLC_FLUSH_IF_EMPTY BIT(36)
|
||||
#define ACC_OVRD_DISABLE_RETENTION BIT(37)
|
||||
#define ACC_OVRD_DISABLE_NEXT_POWER_GATE BIT(38)
|
||||
#define ACC_OVRD_AP_SKEW_N_DELAY_CTL BIT(39)
|
||||
#define ACC_OVRD_DISABLE_C1_PPT_THROTTLE_0 BIT(40)
|
||||
#define ACC_OVRD_DISABLE_C1_PPT_THROTTLE_1 BIT(41)
|
||||
#define ACC_OVRD_REVERT_EMA_SEL_TO_H13 BIT(42)
|
||||
#define ACC_OVRD_DISABLE_SO_C_GLOBAL_TIME BIT(43)
|
||||
#define ACC_OVRD_QUIESCE_APSC_BEFORE_ACC_SLEEP BIT(44)
|
||||
#define ACC_OVRD_IVDM_CLK_ROOT_SEL BIT(45)
|
||||
#define ACC_OVRD_MA_WITHOUT_SW_POLLING BIT(46)
|
||||
#define ACC_OVRD_PMGR_UT_ADCLK_CODE ((ULONG(x)) << 47)
|
||||
#define ACC_OVRD_PMGR_UT_ADCLK_CODE_MASK GENMASK(50, 47)
|
||||
#define ACC_OVRD_PMGR_UT_DITHER_CODE ((ULONG(x)) << 51)
|
||||
#define ACC_OVRD_PMGR_UT_DITHER_CODE_MASK GENMASK(54, 51)
|
||||
#define ACC_OVRD_DIVS_UPD_ABRT_LIR BIT(55)
|
||||
#define ACC_OVRD_CNVT_INC_TO_FULL_UPD BIT(56)
|
||||
#define ACC_OVRD_DISABLE_DVTMF BIT(57)
|
||||
#define ACC_OVRD_SKIP_BIU_DI_VS_UPD_ON_FIX_FREQ_RECLOCK BIT(58)
|
||||
#define ACC_OVRD_PWR_UP_DN_CPU_AFTER_ANE_ACK BIT(59)
|
||||
#define ACC_OVRD_ANE_CLOCK_STOP_REF_COUNT ((ULONG(x)) << 60)
|
||||
#define ACC_OVRD_ANE_CLOCK_STOP_REF_COUNT_MASK GENMASK(61, 60)
|
||||
#define ACC_OVRD_SPR_OCLA_SEL ((ULONG(x)) << 62)
|
||||
#define ACC_OVRD_SPR_OCLA_SEL_MASK GENMASK(63, 62)
|
||||
|
||||
#define SYS_IMP_APL_UPMCR0 sys_reg(3, 7, 15, 0, 4)
|
||||
#define UPMCR0_IMODE_OFF (0 << 16)
|
||||
|
|
|
|||
|
|
@ -86,6 +86,7 @@
|
|||
{"name": "PMC8_EVENT_SEL", "msb": 23, "lsb": 16},
|
||||
{"name": "PMC9_EVENT_SEL", "msb": 31, "lsb": 24}
|
||||
]}]},
|
||||
{"index": 0, "name": "PMCR1_GL1", "fullname": "Performance Monitor Control Register 1 (GL1)", "enc": [3, 1, 15, 8, 2 ], "width": 64},
|
||||
{"index": 0, "name": "PMSR_EL1", "fullname": "Performance Monitor Status Register", "enc": [3, 1, 15, 13, 0 ], "width": 64,
|
||||
"fieldsets": [{"fields": [
|
||||
{"name": "PMC0_OVERFLOW", "msb": 0, "lsb": 0},
|
||||
|
|
@ -118,10 +119,12 @@
|
|||
{"index": 0, "name": "FED_ERR_STS_EL1", "fullname": "FED Error Status", "enc": [3, 4, 15, 0, 0 ], "width": 64},
|
||||
{"index": 0, "name": "E_FED_ERR_STS_EL1", "fullname": "FED Error Status (E-Core)", "enc": [3, 4, 15, 0, 2 ], "width": 64},
|
||||
{"index": 0, "name": "APCTL_EL1", "fullname": "Pointer Authentication Control", "enc": [3, 4, 15, 0, 4 ], "width": 64},
|
||||
{"index": 0, "name": "KERNELKEYLO_EL1", "fullname": "Pointer Authentication Kernel Key Low", "enc": [3, 4, 15, 1, 0 ], "width": 64},
|
||||
{"index": 0, "name": "KERNELKEYHI_EL1", "fullname": "Pointer Authentication Kernel Key High", "enc": [3, 4, 15, 1, 1 ], "width": 64},
|
||||
{"index": 0, "name": "SPR_LOCKDOWN_EL1", "fullname": "SPR Lockdown", "enc": [3, 4, 15, 0, 5 ], "width": 64},
|
||||
{"index": 0, "name": "KERNKEYLO_EL1", "fullname": "Pointer Authentication Kernel Key Low", "enc": [3, 4, 15, 1, 0 ], "width": 64},
|
||||
{"index": 0, "name": "KERNKEYHI_EL1", "fullname": "Pointer Authentication Kernel Key High", "enc": [3, 4, 15, 1, 1 ], "width": 64},
|
||||
{"index": 0, "name": "VMSA_LOCK_EL1", "fullname": "Virtual Memory System Architecture Lock", "enc": [3, 4, 15, 1, 2 ], "width": 64},
|
||||
{"index": 0, "name": "AMX_CTL_EL1", "fullname": "AMX Control (EL1)", "enc": [3, 4, 15, 1, 4 ], "width": 64,
|
||||
{"index": 0, "name": "AMX_STATE_EL12", "fullname": "AMX State (EL1)", "enc": [3, 4, 15, 1, 3 ], "width": 64},
|
||||
{"index": 0, "name": "AMX_CONFIG_EL1", "fullname": "AMX Config (EL1)", "enc": [3, 4, 15, 1, 4 ], "width": 64,
|
||||
"fieldsets": [{"fields": [
|
||||
{"name": "EN", "msb": 63, "lsb": 63}
|
||||
]}]},
|
||||
|
|
@ -131,25 +134,32 @@
|
|||
{"index": 0, "name": "CTRR_A_LWR_EL1", "fullname": "CTRR A Lower Address (EL1)", "enc": [3, 4, 15, 2, 3 ], "width": 64},
|
||||
{"index": 0, "name": "CTRR_A_UPR_EL1", "fullname": "CTRR A Upper Address (EL1)", "enc": [3, 4, 15, 2, 4 ], "width": 64},
|
||||
{"index": 0, "name": "CTRR_CTL_EL1", "fullname": "CTRR Control (EL1)", "enc": [3, 4, 15, 2, 5 ], "width": 64},
|
||||
{"index": 0, "name": "APRR_JIT_ENABLE_EL2", "fullname": "APRR JIT Enable", "enc": [3, 4, 15, 2, 6 ], "width": 64},
|
||||
{"index": 0, "name": "VMSA_LOCK_EL12", "fullname": "Virtual Memory System Architecture Lock (EL12)", "enc": [3, 4, 15, 2, 6 ], "width": 64},
|
||||
{"index": 0, "name": "APRR_JIT_MASK_EL2", "fullname": "APRR JIT Mask", "enc": [3, 4, 15, 2, 7 ], "width": 64},
|
||||
{"index": 0, "name": "AMX_CTL_EL12", "fullname": "AMX Control (EL12)", "enc": [3, 4, 15, 4, 6 ], "width": 64},
|
||||
{"index": 0, "name": "AMX_CONFIG_EL12", "fullname": "AMX Config (EL12)", "enc": [3, 4, 15, 4, 6 ], "width": 64},
|
||||
{"index": 0, "name": "AMX_CTL_EL2", "fullname": "AMX Control (EL2)", "enc": [3, 4, 15, 4, 7 ], "width": 64,
|
||||
"fieldsets": [{"fields": [
|
||||
{"name": "EN", "msb": 63, "lsb": 63},
|
||||
{"name": "EN_EL1", "msb": 62, "lsb": 62}
|
||||
]}]},
|
||||
{"index": 0, "name": "SPRR_PERM_EL20_SILLY_THING", "fullname": "SPRR Permission Configuration Register (EL20, useless)", "enc": [3, 4, 15, 5, 1 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_PERM_EL02", "fullname": "SPRR Permission Configuration Register (EL02)", "enc": [3, 4, 15, 5, 2 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_KMASK0_EL12", "fullname": "SPRR Kernel Permission Unlock Mask (EL12)", "enc": [3, 4, 15, 6, 0 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UMASK0_EL2", "fullname": "SPRR Permission Unlock Mask 0 (EL2)", "enc": [3, 4, 15, 7, 0 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UMASK1_EL2", "fullname": "SPRR Permission Unlock Mask 1 (EL2)", "enc": [3, 4, 15, 7, 1 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UMASK2_EL2", "fullname": "SPRR Permission Unlock Mask 2 (EL2)", "enc": [3, 4, 15, 7, 2 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UMASK3_EL2", "fullname": "SPRR Permission Unlock Mask 3 (EL2)", "enc": [3, 4, 15, 7, 3 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UMASK0_EL12", "fullname": "SPRR Permission Unlock Mask 0 (EL12)", "enc": [3, 4, 15, 8, 0 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UMASK1_EL12", "fullname": "SPRR Permission Unlock Mask 1 (EL12)", "enc": [3, 4, 15, 8, 1 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UMASK2_EL12", "fullname": "SPRR Permission Unlock Mask 2 (EL12)", "enc": [3, 4, 15, 8, 2 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UMASK3_EL12", "fullname": "SPRR Permission Unlock Mask 3 (EL12)", "enc": [3, 4, 15, 8, 3 ], "width": 32},
|
||||
{"index": 0, "name": "CORE_INDEX", "fullname": "Core index in cluster", "enc": [3, 4, 15, 5, 0 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_PPERM_EL20_SILLY_THING", "fullname": "SPRR Permission Configuration Register (EL20, useless)", "enc": [3, 4, 15, 5, 1 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_UPERM_EL02", "fullname": "SPRR User Permission Configuration Register (EL02)", "enc": [3, 4, 15, 5, 2 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_UMPRR_EL2", "fullname": "SPRR User MPRR (EL2)", "enc": [3, 4, 15, 7, 0 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UPERM_SH1_EL2", "fullname": "SPRR User Permission SH1 (EL2)", "enc": [3, 4, 15, 7, 1 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UPERM_SH2_EL2", "fullname": "SPRR User Permission SH2 (EL2)", "enc": [3, 4, 15, 7, 2 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UPERM_SH3_EL2", "fullname": "SPRR User Permission SH3 (EL2)", "enc": [3, 4, 15, 7, 3 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UMPRR_EL12", "fullname": "SPRR User MPRR (EL12)", "enc": [3, 4, 15, 8, 0 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UPERM_SH1_EL12", "fullname": "SPRR User Permission SH1 (EL12)", "enc": [3, 4, 15, 8, 1 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UPERM_SH2_EL12", "fullname": "SPRR User Permission SH2 (EL12)", "enc": [3, 4, 15, 8, 2 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UPERM_SH3_EL12", "fullname": "SPRR User Permission SH3 (EL12)", "enc": [3, 4, 15, 8, 3 ], "width": 32},
|
||||
{"index": 0, "name": "CTRR_A_LWR_EL12", "fullname": "CTRR A Lower Address (EL12)", "enc": [3, 4, 15, 9, 0 ], "width": 64},
|
||||
{"index": 0, "name": "CTRR_A_UPR_EL12", "fullname": "CTRR A Upper Address (EL12)", "enc": [3, 4, 15, 9, 1 ], "width": 64},
|
||||
{"index": 0, "name": "CTRR_B_LWR_EL12", "fullname": "CTRR B Lower Address (EL12)", "enc": [3, 4, 15, 9, 2 ], "width": 64},
|
||||
{"index": 0, "name": "CTRR_B_UPR_EL12", "fullname": "CTRR B Upper Address (EL12)", "enc": [3, 4, 15, 9, 3 ], "width": 64},
|
||||
{"index": 0, "name": "CTRR_CTL_EL12", "fullname": "CTRR Control (EL12)", "enc": [3, 4, 15, 9, 4 ], "width": 64},
|
||||
{"index": 0, "name": "CTRR_LOCK_EL12", "fullname": "CTRR Lock (EL12)", "enc": [3, 4, 15, 9, 5 ], "width": 64},
|
||||
{"index": 0, "name": "SIQ_CFG_EL1", "fullname": "System Interrupt Configuration (EL1)", "enc": [3, 4, 15, 10, 4 ], "width": 64},
|
||||
{"index": 0, "name": "ACNTPCT_EL0", "fullname": "Physical timer counter register (pre-spec CNTPCTSS_EL0)", "enc": [3, 4, 15, 10, 5 ], "width": 64},
|
||||
{"index": 0, "name": "ACNTVCT_EL0", "fullname": "Virtual timer counter register (pre-spec CNTVCTSS_EL0)", "enc": [3, 4, 15, 10, 6 ], "width": 64},
|
||||
{"index": 0, "name": "CTRR_A_LWR_EL2", "fullname": "CTRR A Lower Address (EL2)", "enc": [3, 4, 15, 11, 0 ], "width": 64},
|
||||
|
|
@ -170,6 +180,7 @@
|
|||
{"name": "ENA_V", "msb": 0, "lsb": 0},
|
||||
{"name": "ENA_P", "msb": 1, "lsb": 1}
|
||||
]}]},
|
||||
{"index": 0, "name": "AWL_SCRATCH_EL1", "fullname": "AWL Scratch Register", "enc": [3, 5, 15, 2, 6 ], "width": 64},
|
||||
{"index": 0, "name": "IPI_CR_EL1", "fullname": "IPI Control Register", "enc": [3, 5, 15, 3, 1 ], "width": 64},
|
||||
{"index": 0, "name": "ACC_CFG_EL1", "fullname": "Apple Core Cluster Configuration", "enc": [3, 5, 15, 4, 0 ], "width": 64},
|
||||
{"index": 0, "name": "CYC_OVRD_EL1", "fullname": "Cyclone Override", "enc": [3, 5, 15, 5, 0 ], "width": 64},
|
||||
|
|
@ -190,34 +201,34 @@
|
|||
"fieldsets": [{"fields": [
|
||||
{"name": "EN", "msb": 0, "lsb": 0}
|
||||
]}]},
|
||||
{"index": 0, "name": "SPRR_UNK1_EL1", "fullname": "SPRR Unknown (EL1)", "enc": [3, 6, 15, 1, 3 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_AMRANGE_EL1", "fullname": "SPRR AM Range (EL1)", "enc": [3, 6, 15, 1, 3 ], "width": 64},
|
||||
{"index": 0, "name": "GXF_CONFIG_EL2", "fullname": "GXF Configuration Register (EL2)", "enc": [3, 6, 15, 1, 4 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_PERM_EL0", "fullname": "SPRR Permission Configuration Register (EL0)", "enc": [3, 6, 15, 1, 5 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_PERM_EL1", "fullname": "SPRR Permission Configuration Register (EL1)", "enc": [3, 6, 15, 1, 6 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_PERM_EL2", "fullname": "SPRR Permission Configuration Register (EL2)", "enc": [3, 6, 15, 1, 7 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_UPERM_EL0", "fullname": "SPRR User Permission Configuration Register (EL0)", "enc": [3, 6, 15, 1, 5 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_PPERM_EL1", "fullname": "SPRR Kernel Permission Configuration Register (EL1)", "enc": [3, 6, 15, 1, 6 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_PPERM_EL2", "fullname": "SPRR Kernel Permission Configuration Register (EL2)", "enc": [3, 6, 15, 1, 7 ], "width": 64},
|
||||
{"index": 0, "name": "E_MMU_ERR_STS_EL1", "fullname": "MMU Error Status (E-Core)", "enc": [3, 6, 15, 2, 0 ], "width": 64},
|
||||
{"index": 0, "name": "APGAKeyLo_EL12", "fullname": "Pointer Authentication Key A for Code Low (EL12)", "enc": [3, 6, 15, 2, 1 ], "width": 64},
|
||||
{"index": 0, "name": "APGAKeyHi_EL12", "fullname": "Pointer Authentication Key A for Code High (EL12)", "enc": [3, 6, 15, 2, 2 ], "width": 64},
|
||||
{"index": 0, "name": "KERNELKEYLO_EL12", "fullname": "Pointer Authentication Kernel Key Low (EL12)", "enc": [3, 6, 15, 2, 3 ], "width": 64},
|
||||
{"index": 0, "name": "KERNELKEYHI_EL12", "fullname": "Pointer Authentication Kernel Key High (EL12)", "enc": [3, 6, 15, 2, 4 ], "width": 64},
|
||||
{"index": 0, "name": "KERNKEYLO_EL12", "fullname": "Pointer Authentication Kernel Key Low (EL12)", "enc": [3, 6, 15, 2, 3 ], "width": 64},
|
||||
{"index": 0, "name": "KERNKEYHI_EL12", "fullname": "Pointer Authentication Kernel Key High (EL12)", "enc": [3, 6, 15, 2, 4 ], "width": 64},
|
||||
{"index": 0, "name": "AFPCR_EL0", "fullname": "Apple Floating-Point Control Register", "enc": [3, 6, 15, 2, 5 ], "width": 64},
|
||||
{"index": 0, "name": "AIDR2_EL1", "fullname": "Apple ID Register 2", "enc": [3, 6, 15, 2, 7 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_UMASK0_EL1", "fullname": "SPRR Permission Unlock Mask 0 (EL1)", "enc": [3, 6, 15, 3, 0 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_KMASK0_EL1", "fullname": "SPRR Kernel Permission Unlock Mask 0 (EL1)", "enc": [3, 6, 15, 3, 1 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_KMASK0_EL2", "fullname": "SPRR Kernel Permission Unlock Mask 0 (EL2)", "enc": [3, 6, 15, 3, 2 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UMASK1_EL1", "fullname": "SPRR Permission Unlock Mask 1 (EL1)", "enc": [3, 6, 15, 3, 3 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UMASK2_EL1", "fullname": "SPRR Permission Unlock Mask 2 (EL1)", "enc": [3, 6, 15, 3, 4 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UMASK3_EL1", "fullname": "SPRR Permission Unlock Mask 3 (EL1)", "enc": [3, 6, 15, 3, 5 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_KMASK1_EL1", "fullname": "SPRR Kernel Permission Unlock Mask 1 (EL12)", "enc": [3, 6, 15, 4, 2 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_KMASK2_EL1", "fullname": "SPRR Kernel Permission Unlock Mask 2 (EL12)", "enc": [3, 6, 15, 4, 3 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_KMASK3_EL1", "fullname": "SPRR Kernel Permission Unlock Mask 3 (EL12)", "enc": [3, 6, 15, 4, 4 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_KMASK1_EL2", "fullname": "SPRR Kernel Permission Unlock Mask 1 (EL12)", "enc": [3, 6, 15, 5, 1 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_KMASK2_EL2", "fullname": "SPRR Kernel Permission Unlock Mask 2 (EL12)", "enc": [3, 6, 15, 5, 2 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_KMASK3_EL2", "fullname": "SPRR Kernel Permission Unlock Mask 3 (EL12)", "enc": [3, 6, 15, 5, 3 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_KMASK0_EL12", "fullname": "SPRR Kernel Permission Unlock Mask 0 (EL12)", "enc": [3, 6, 15, 6, 0 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_KMASK1_EL12", "fullname": "SPRR Kernel Permission Unlock Mask 1 (EL12)", "enc": [3, 6, 15, 6, 1 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_KMASK2_EL12", "fullname": "SPRR Kernel Permission Unlock Mask 2 (EL12)", "enc": [3, 6, 15, 6, 2 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_KMASK3_EL12", "fullname": "SPRR Kernel Permission Unlock Mask 3 (EL12)", "enc": [3, 6, 15, 6, 3 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UMPRR_EL1", "fullname": "SPRR User MPRR (EL1)", "enc": [3, 6, 15, 3, 0 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_PMPRR_EL1", "fullname": "SPRR Kernel MPRR (EL1)", "enc": [3, 6, 15, 3, 1 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_PMPRR_EL2", "fullname": "SPRR Kernel MPRR (EL2)", "enc": [3, 6, 15, 3, 2 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UPERM_SH1_EL1", "fullname": "SPRR User Permission SH1 (EL1)", "enc": [3, 6, 15, 3, 3 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UPERM_SH2_EL1", "fullname": "SPRR User Permission SH2 (EL1)", "enc": [3, 6, 15, 3, 4 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_UPERM_SH3_EL1", "fullname": "SPRR User Permission SH3 (EL1)", "enc": [3, 6, 15, 3, 5 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_PPERM_SH1_EL1", "fullname": "SPRR Kernel Permission SH1 (EL1)", "enc": [3, 6, 15, 4, 2 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_PPERM_SH2_EL1", "fullname": "SPRR Kernel Permission SH2 (EL1)", "enc": [3, 6, 15, 4, 3 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_PPERM_SH3_EL1", "fullname": "SPRR Kernel Permission SH3 (EL1)", "enc": [3, 6, 15, 4, 4 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_PPERM_SH1_EL2", "fullname": "SPRR Kernel Permission SH1 (EL2)", "enc": [3, 6, 15, 5, 1 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_PPERM_SH2_EL2", "fullname": "SPRR Kernel Permission SH2 (EL2)", "enc": [3, 6, 15, 5, 2 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_PPERM_SH3_EL2", "fullname": "SPRR Kernel Permission SH3 (EL2)", "enc": [3, 6, 15, 5, 3 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_PMPRR_EL12", "fullname": "SPRR Kernel MPRR (EL12)", "enc": [3, 6, 15, 6, 0 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_PPERM_SH1_EL12", "fullname": "SPRR Kernel Permission SH1 (EL12)", "enc": [3, 6, 15, 6, 1 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_PPERM_SH2_EL12", "fullname": "SPRR Kernel Permission SH2 (EL12)", "enc": [3, 6, 15, 6, 2 ], "width": 32},
|
||||
{"index": 0, "name": "SPRR_PPERM_SH3_EL12", "fullname": "SPRR Kernel Permission SH3 (EL12)", "enc": [3, 6, 15, 6, 3 ], "width": 32},
|
||||
{"index": 0, "name": "APIAKeyLo_EL12", "fullname": "Pointer Authentication Key A for Instruction Low (EL12)", "enc": [3, 6, 15, 7, 0 ], "width": 64},
|
||||
{"index": 0, "name": "APIAKeyHi_EL12", "fullname": "Pointer Authentication Key A for Instruction High (EL12)", "enc": [3, 6, 15, 7, 1 ], "width": 64},
|
||||
{"index": 0, "name": "APIBKeyLo_EL12", "fullname": "Pointer Authentication Key A for Instruction Low (EL12)", "enc": [3, 6, 15, 7, 2 ], "width": 64},
|
||||
|
|
@ -226,17 +237,19 @@
|
|||
{"index": 0, "name": "APDAKeyHi_EL12", "fullname": "Pointer Authentication Key A for Data High (EL12)", "enc": [3, 6, 15, 7, 5 ], "width": 64},
|
||||
{"index": 0, "name": "APDBKeyLo_EL12", "fullname": "Pointer Authentication Key A for Data Low (EL12)", "enc": [3, 6, 15, 7, 6 ], "width": 64},
|
||||
{"index": 0, "name": "APDBKeyHi_EL12", "fullname": "Pointer Authentication Key A for Data High (EL12)", "enc": [3, 6, 15, 7, 7 ], "width": 64},
|
||||
{"index": 0, "name": "GXF_STATUS_EL1", "fullname": "GXF Status Register", "enc": [3, 6, 15, 8, 0 ], "width": 64,
|
||||
{"index": 0, "name": "GXF_STATUS_EL1", "fullname": "GXF Status Register (CurrentG)", "enc": [3, 6, 15, 8, 0 ], "width": 64,
|
||||
"fieldsets": [{"fields": [
|
||||
{"name": "GUARDED", "msb": 0, "lsb": 0}
|
||||
]}]},
|
||||
{"index": 0, "name": "GXF_ENTER_EL1", "fullname": "GXF genter Entry Vector Register (EL1)", "enc": [3, 6, 15, 8, 1 ], "width": 64},
|
||||
{"index": 0, "name": "GXF_ABORT_EL1", "fullname": "GXF Abort Vector Register (EL1)", "enc": [3, 6, 15, 8, 2 ], "width": 64},
|
||||
{"index": 0, "name": "GXF_ENTRY_EL1", "fullname": "GXF genter Entry Vector Register (EL1)", "enc": [3, 6, 15, 8, 1 ], "width": 64},
|
||||
{"index": 0, "name": "GXF_PABENTRY_EL1", "fullname": "GXF Abort Vector Register (EL1)", "enc": [3, 6, 15, 8, 2 ], "width": 64},
|
||||
{"index": 0, "name": "ASPSR_EL1", "fullname": "ASPSR (EL1)", "enc": [3, 6, 15, 8, 3 ], "width": 64},
|
||||
{"index": 0, "name": "VBAR_GL12", "fullname": "Vector Base Address Register (GL12)", "enc": [3, 6, 15, 9, 2 ], "width": 64},
|
||||
{"index": 0, "name": "SPSR_GL12", "fullname": "Saved Program Status Register (GL12)", "enc": [3, 6, 15, 9, 3 ], "width": 64},
|
||||
{"index": 0, "name": "ASPSR_GL12", "fullname": "ASPSR (GL12)", "enc": [3, 6, 15, 9, 4 ], "width": 64},
|
||||
{"index": 0, "name": "ESR_GL12", "fullname": "Exception Syndrome Register (GL12)", "enc": [3, 6, 15, 9, 5 ], "width": 64},
|
||||
{"index": 0, "name": "ELR_GL12", "fullname": "Exception Link Register (GL12)", "enc": [3, 6, 15, 9, 6 ], "width": 64},
|
||||
{"index": 0, "name": "FAR_GL12", "fullname": "Fault Address Register (GL12)", "enc": [3, 6, 15, 9, 7 ], "width": 64},
|
||||
{"index": 0, "name": "SP_GL12", "fullname": "Stack Pointer Register (GL12)", "enc": [3, 6, 15, 10, 0 ], "width": 64},
|
||||
{"index": 0, "name": "TPIDR_GL1", "fullname": "Software Thread ID Register (GL1)", "enc": [3, 6, 15, 10, 1 ], "width": 64},
|
||||
{"index": 0, "name": "VBAR_GL1", "fullname": "Vector Base Address Register (GL1)", "enc": [3, 6, 15, 10, 2 ], "width": 64},
|
||||
|
|
@ -252,24 +265,24 @@
|
|||
{"index": 0, "name": "ESR_GL2", "fullname": "Exception Syndrome Register (GL2)", "enc": [3, 6, 15, 11, 5 ], "width": 64},
|
||||
{"index": 0, "name": "ELR_GL2", "fullname": "Exception Link Register (GL2)", "enc": [3, 6, 15, 11, 6 ], "width": 64},
|
||||
{"index": 0, "name": "FAR_GL2", "fullname": "Fault Address Register (GL2)", "enc": [3, 6, 15, 11, 7 ], "width": 64},
|
||||
{"index": 0, "name": "GXF_ENTER_EL2", "fullname": "GXF genter Entry Vector Register (EL2)", "enc": [3, 6, 15, 12, 0 ], "width": 64},
|
||||
{"index": 0, "name": "GXF_ABORT_EL2", "fullname": "GXF Abort Vector Register (EL2)", "enc": [3, 6, 15, 12, 1 ], "width": 64},
|
||||
{"index": 0, "name": "GXF_ENTRY_EL2", "fullname": "GXF genter Entry Vector Register (EL2)", "enc": [3, 6, 15, 12, 0 ], "width": 64},
|
||||
{"index": 0, "name": "GXF_PABENTRY_EL2", "fullname": "GXF Abort Vector Register (EL2)", "enc": [3, 6, 15, 12, 1 ], "width": 64},
|
||||
{"index": 0, "name": "APCTL_EL2", "fullname": "Pointer Authentication Control (EL2)", "enc": [3, 6, 15, 12, 2 ], "width": 64},
|
||||
{"index": 0, "name": "APSTS_EL2_MAYBE", "fullname": "Pointer Authentication Status (EL2, maybe)", "enc": [3, 6, 15, 12, 3 ], "width": 64},
|
||||
{"index": 0, "name": "APSTS_EL1", "fullname": "Pointer Authentication Status", "enc": [3, 6, 15, 12, 4 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_CONFIG_EL2", "fullname": "SPRR Configuration Register (EL2)", "enc": [3, 6, 15, 14, 2 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_UNK1_EL2", "fullname": "SPRR Unknown (EL2)", "enc": [3, 6, 15, 14, 3 ], "width": 64},
|
||||
{"index": 0, "name": "APVMKEYLO_EL2", "fullname": "Pointer Authentication VM Machine Key Low", "enc": [3, 6, 15, 14, 4 ], "width": 64},
|
||||
{"index": 0, "name": "APVMKEYHI_EL2", "fullname": "Pointer Authentication VM Machine Key High", "enc": [3, 6, 15, 14, 5 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_AMRANGE_EL2", "fullname": "SPRR AM Range (EL2)", "enc": [3, 6, 15, 14, 3 ], "width": 64},
|
||||
{"index": 0, "name": "VMKEYLO_EL2", "fullname": "Pointer Authentication VM Machine Key Low", "enc": [3, 6, 15, 14, 4 ], "width": 64},
|
||||
{"index": 0, "name": "VMKEYHI_EL2", "fullname": "Pointer Authentication VM Machine Key High", "enc": [3, 6, 15, 14, 5 ], "width": 64},
|
||||
{"index": 0, "name": "ACTLR_EL12", "fullname": "Auxiliary Control Register (EL12)", "enc": [3, 6, 15, 14, 6 ], "width": 64},
|
||||
{"index": 0, "name": "APSTS_EL12", "fullname": "Pointer Authentication Status (EL12)", "enc": [3, 6, 15, 14, 7 ], "width": 64},
|
||||
{"index": 0, "name": "APCTL_EL12", "fullname": "Pointer Authentication Control (EL12)", "enc": [3, 6, 15, 15, 0 ], "width": 64},
|
||||
{"index": 0, "name": "GXF_CONFIG_EL12", "fullname": "GXF Configuration Register (EL12)", "enc": [3, 6, 15, 15, 1 ], "width": 64},
|
||||
{"index": 0, "name": "GXF_ENTER_EL12", "fullname": "GXF genter Entry Vector Register (EL12)", "enc": [3, 6, 15, 15, 2 ], "width": 64},
|
||||
{"index": 0, "name": "GXF_ABORT_EL12", "fullname": "GXF Abort Vector Register (EL12)", "enc": [3, 6, 15, 15, 3 ], "width": 64},
|
||||
{"index": 0, "name": "GXF_ENTRY_EL12", "fullname": "GXF genter Entry Vector Register (EL12)", "enc": [3, 6, 15, 15, 2 ], "width": 64},
|
||||
{"index": 0, "name": "GXF_PABENTRY_EL12", "fullname": "GXF Abort Vector Register (EL12)", "enc": [3, 6, 15, 15, 3 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_CONFIG_EL12", "fullname": "SPRR Configuration Register (EL12)", "enc": [3, 6, 15, 15, 4 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_UNK1_EL12", "fullname": "SPRR Unknown (EL2)", "enc": [3, 6, 15, 15, 5 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_PERM_EL12", "fullname": "SPRR Permission Configuration Register (EL12)", "enc": [3, 6, 15, 15, 7 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_AMRANGE_EL12", "fullname": "SPRR AM Range (EL12)", "enc": [3, 6, 15, 15, 5 ], "width": 64},
|
||||
{"index": 0, "name": "SPRR_PPERM_EL12", "fullname": "SPRR Permission Configuration Register (EL12)", "enc": [3, 6, 15, 15, 7 ], "width": 64},
|
||||
{"index": 0, "name": "UPMCR0_EL1", "fullname": "Uncore Performance Monitor Control Register 0", "enc": [3, 7, 15, 0, 4 ], "width": 64},
|
||||
{"index": 0, "name": "UPMESR0_EL1", "fullname": "Uncore Performance Monitor Event Selection Register 0", "enc": [3, 7, 15, 1, 4 ], "width": 64},
|
||||
{"index": 0, "name": "UPMECM0_EL1", "fullname": "Uncore Performance Monitor Event Core Mask 0", "enc": [3, 7, 15, 3, 4 ], "width": 64},
|
||||
|
|
|
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Loading…
Reference in a new issue