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MMU: set better defaults for TCR_EL2

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Signed-off-by: Sven Peter <sven@svenpeter.dev>
This commit is contained in:
Sven Peter 2021-01-23 23:25:49 +01:00 committed by Hector Martin
parent c9f975f886
commit 559fdb85e2
2 changed files with 16 additions and 4 deletions
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3
src/memory.c
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@ -206,7 +206,8 @@ static void _mmu_configure(void)
msr(MAIR_EL2, (MAIR_ATTR_NORMAL_DEFAULT << MAIR_SHIFT_NORMAL) |
(MAIR_ATTR_DEVICE_nGnRnE << MAIR_SHIFT_DEVICE_nGnRnE) |
(MAIR_ATTR_DEVICE_nGnRE << MAIR_SHIFT_DEVICE_nGnRE));
msr(TCR_EL2, TG0_16K | PS_1TB);
msr(TCR_EL2, TCR_TG0_16K | TCR_PS_1TB | TCR_SH0_IS | TCR_ORGN0_WBWA |
TCR_IRGN0_WBWA | TCR_T0SZ_48BIT);
msr(TTBR0_EL2, (uintptr_t)__pagetable_L0);
// Armv8-A Address Translation, 100940_0101_en, page 28

17
src/memory.h
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@ -24,10 +24,21 @@
#define SCTLR_M (1UL)
/*
* https://developer.arm.com/documentation/100442/0100/register-descriptions/aarch64-system-registers/tcr-el2--translation-control-register--el2
* https://developer.arm.com/docs/ddi0595/h/aarch64-system-registers/tcr_el2
* TCR_PS_1TB selects 40 bits/1TB physical address size (TODO: is this correct?)
* TCR_TG0_16K selects 16K pages
* TCR_SH0_IS marks memory used during translation table walks as inner sharable
* TCR_ORGN0_WBWA and TCR_IRGN0_WBWA set the cacheability atrributes for memory
* used during translation table walks to Inner/Outer
* Write-Back Read-Allocate Write-Allocate Cacheable
* TCR_T0SZ_48BIT selects 48bit virtual addresses
*/
#define PS_1TB ((0b010UL) << 16)
#define TG0_16K ((0b10UL) << 14)
#define TCR_PS_1TB ((0b010UL) << 16)
#define TCR_TG0_16K ((0b10UL) << 14)
#define TCR_SH0_IS ((0b11UL) << 12)
#define TCR_ORGN0_WBWA ((0b01UL) << 10)
#define TCR_IRGN0_WBWA ((0b01UL) << 8)
#define TCR_T0SZ_48BIT ((16UL) << 0)
/*
* aarch64 allows to configure attribute sets for up to eight different memory