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https://github.com/AsahiLinux/m1n1
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m1n1.agx.shim: New module
Signed-off-by: Asahi Lina <lina@asahilina.net>
This commit is contained in:
Asahi Lina
parent
51abb9082e
commit
512982f4aa
1 changed files with 314 additions and 0 deletions
314
proxyclient/m1n1/agx/shim.py
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314
proxyclient/m1n1/agx/shim.py
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#!/usr/bin/env python3
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# SPDX-License-Identifier: MIT
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import errno, ctypes, sys, atexit
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from construct import *
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from m1n1 import malloc
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from m1n1.utils import Register32
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from m1n1.constructutils import ConstructClass
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from m1n1.agx import AGX
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from m1n1.agx.render import *
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from m1n1.proxyutils import *
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from m1n1.utils import *
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PAGE_SIZE = 32768
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SHIM_MEM_SIZE = 4 * 1024 * 1024 * 1024
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class IOCTL(Register32):
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NR = 7, 0
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TYPE = 15, 8
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SIZE = 29, 16
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DIR = 31, 30
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_IOC_NONE = 0
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_IOC_WRITE = 1
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_IOC_READ = 2
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_IO = lambda type, nr: IOCTL(TYPE=type, NR=nr, SIZE=0, DIR=_IOC_NONE)
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_IOR = lambda type, nr, size: IOCTL(TYPE=type, NR=nr, SIZE=size, DIR=_IOC_READ)
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_IOW = lambda type, nr, size: IOCTL(TYPE=type, NR=nr, SIZE=size, DIR=_IOC_WRITE)
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_IOWR = lambda type, nr, size: IOCTL(TYPE=type, NR=nr, SIZE=size, DIR=_IOC_READ|_IOC_WRITE)
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DRM_IOCTL_BASE = ord('d')
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ASAHI_BO_PIPELINE = 1
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def IO(nr):
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def dec(f):
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f._ioctl = _IO(DRM_IOCTL_BASE, nr)
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return f
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return dec
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def IOR(nr, cls):
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def dec(f):
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f._ioctl = _IOR(DRM_IOCTL_BASE, nr, cls.sizeof())
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f._arg_cls = cls
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return f
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return dec
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def IOW(nr, cls):
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def dec(f):
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f._ioctl = _IOW(DRM_IOCTL_BASE, nr, cls.sizeof())
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f._arg_cls = cls
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return f
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return dec
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def IOWR(nr, cls):
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def dec(f):
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f._ioctl = _IOWR(DRM_IOCTL_BASE, nr, cls.sizeof())
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f._arg_cls = cls
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return f
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return dec
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DRM_COMMAND_BASE = 0x40
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class drm_asahi_submit_t(ConstructClass):
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subcon = Struct(
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"cmdbuf" / Int64ul,
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"in_syncs" / Int64ul,
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"in_sync_count" / Int32ul,
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"out_sync" / Int32ul,
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)
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class drm_asahi_wait_bo_t(ConstructClass):
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subcon = Struct(
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"handle" / Int32ul,
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Padding(4),
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"timeout_ns" / Int64sl,
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)
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class drm_asahi_create_bo_t(ConstructClass):
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subcon = Struct(
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"size" / Int32ul,
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"flags" / Int32ul,
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"handle" / Int32ul,
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Padding(4),
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"offset" / Int64ul,
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)
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#class drm_asahi_mmap_bo_t(ConstructClass):
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#subcon = Struct(
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#"handle" / Int32ul,
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#"flags" / Int32ul,
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#"offset" / Int64ul,
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#)
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class drm_asahi_get_param_t(ConstructClass):
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subcon = Struct(
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"param" / Int32ul,
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Padding(4),
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"value" / Int64ul,
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)
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class drm_asahi_get_bo_offset_t(ConstructClass):
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subcon = Struct(
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"handle" / Int32ul,
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Padding(4),
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"offset" / Int64ul,
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)
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ASAHI_MAX_ATTACHMENTS = 16
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ASAHI_ATTACHMENT_C = 0
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ASAHI_ATTACHMENT_Z = 1
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ASAHI_ATTACHMENT_S = 2
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class drm_asahi_attachment_t(ConstructClass):
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subcon = Struct(
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"type" / Int32ul,
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"size" / Int32ul,
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"pointer" / Int64ul,
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)
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ASAHI_CMDBUF_LOAD_C = (1 << 0)
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ASAHI_CMDBUF_LOAD_Z = (1 << 1)
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ASAHI_CMDBUF_LOAD_S = (1 << 2)
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class drm_asahi_cmdbuf_t(ConstructClass):
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subcon = Struct(
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"flags" / Int64ul,
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"encoder_ptr" / Int64ul,
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"encoder_id" / Int32ul,
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"cmd_ta_id" / Int32ul,
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"cmd_3d_id" / Int32ul,
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"ds_flags" / Int32ul,
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"depth_buffer" / Int64ul,
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"stencil_buffer" / Int64ul,
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"scissor_array" / Int64ul,
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"depth_bias_array" / Int64ul,
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"fb_width" / Int32ul,
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"fb_height" / Int32ul,
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"load_pipeline" / Int32ul,
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"load_pipeline_bind" / Int32ul,
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"store_pipeline" / Int32ul,
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"store_pipeline_bind" / Int32ul,
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"partial_reload_pipeline" / Int32ul,
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"partial_reload_pipeline_bind" / Int32ul,
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"partial_store_pipeline" / Int32ul,
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"partial_store_pipeline_bind" / Int32ul,
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"depth_clear_value" / Float32l,
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"stencil_clear_value" / Int8ul,
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Padding(3),
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"attachments" / Array(ASAHI_MAX_ATTACHMENTS, drm_asahi_attachment_t),
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"attachment_count" / Int32ul,
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)
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class DRMAsahiShim:
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def __init__(self, memfd):
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self.memfd = open(memfd, closefd=False, mode="r+b")
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self.initialized = False
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self.ioctl_map = {}
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for key in dir(self):
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f = getattr(self, key)
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ioctl = getattr(f, "_ioctl", None)
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if ioctl is not None:
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self.ioctl_map[ioctl.value] = ioctl, f
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self.bos = {}
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self.pull_buffers = False
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def read_buf(self, ptr, size):
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return ctypes.cast(ptr, ctypes.POINTER(ctypes.c_ubyte * size))[0]
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def init_agx(self):
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from m1n1.setup import p, u, iface
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from m1n1.shell import run_shell
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from m1n1.hw.pmu import PMU
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PMU(u).reset_panic_counter()
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p.pmgr_adt_clocks_enable("/arm-io/gfx-asc")
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p.pmgr_adt_clocks_enable("/arm-io/sgx")
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self.agx = agx = AGX(u)
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mon = RegMonitor(u, ascii=True, bufsize=0x8000000)
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agx.mon = mon
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sgx = agx.sgx_dev
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#mon.add(sgx.gpu_region_base, sgx.gpu_region_size, "contexts")
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#mon.add(sgx.gfx_shared_region_base, sgx.gfx_shared_region_size, "gfx-shared")
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#mon.add(sgx.gfx_handoff_base, sgx.gfx_handoff_size, "gfx-handoff")
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#mon.add(agx.initdasgx.gfx_handoff_base, sgx.gfx_handoff_size, "gfx-handoff")
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atexit.register(p.reboot)
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agx.start()
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def init(self):
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if self.initialized:
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return
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self.init_agx()
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self.renderer = GPURenderer(self.agx)
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self.initialized = True
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@IOW(DRM_COMMAND_BASE + 0x00, drm_asahi_submit_t)
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def submit(self, fd, args):
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#print("Submit!")
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sys.stdout.write(".")
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sys.stdout.flush()
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size = drm_asahi_cmdbuf_t.sizeof()
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cmdbuf = drm_asahi_cmdbuf_t.parse(self.read_buf(args.cmdbuf, size))
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#print(cmdbuf)
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for obj in self.bos.values():
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self.memfd.seek(obj._memfd_offset)
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obj.val = self.memfd.read(obj._size)
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obj.push(True)
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self.renderer.submit(cmdbuf)
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if self.pull_buffers:
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for i in cmdbuf.attachments:
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for obj in self.bos.values():
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if obj._addr == i.pointer:
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obj.pull()
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self.memfd.seek(obj._memfd_offset)
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self.memfd.write(obj.val)
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return 0
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@IOW(DRM_COMMAND_BASE + 0x01, drm_asahi_wait_bo_t)
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def wait_bo(self, fd, args):
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print("Wait BO!", args)
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return 0
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@IOWR(DRM_COMMAND_BASE + 0x02, drm_asahi_create_bo_t)
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def create_bo(self, fd, args):
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memfd_offset = args.offset
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if args.flags & ASAHI_BO_PIPELINE:
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alloc = self.renderer.ctx.pobj
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else:
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alloc = self.renderer.ctx.uobj
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obj = alloc.new(HexDump(Bytes(args.size)), name=f"GBM offset {memfd_offset:#x}", track=False)
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obj._memfd_offset = memfd_offset
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self.bos[memfd_offset] = obj
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args.offset = obj._addr
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if args.flags & ASAHI_BO_PIPELINE:
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args.offset -= self.renderer.ctx.pipeline_base
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print(f"Create BO @ {memfd_offset:#x}")
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return 0
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@IOWR(DRM_COMMAND_BASE + 0x04, drm_asahi_get_param_t)
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def get_param(self, fd, args):
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print("Get Param!", args)
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return 0
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@IOWR(DRM_COMMAND_BASE + 0x05, drm_asahi_get_bo_offset_t)
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def get_bo_offset(self, fd, args):
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print("Get BO Offset!", args)
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return 0
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def bo_free(self, memfd_offset):
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print(f"Free BO @ {memfd_offset:#x}")
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self.bos[memfd_offset].free()
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del self.bos[memfd_offset]
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def ioctl(self, fd, request, p_arg):
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self.init()
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p_arg = ctypes.c_void_p(p_arg)
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if request not in self.ioctl_map:
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print(f"Unknown ioctl: fd={fd} request={IOCTL(request)} arg={p_arg:#x}")
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return -errno.ENOSYS
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ioctl, f = self.ioctl_map[request]
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size = ioctl.SIZE
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if ioctl.DIR & _IOC_WRITE:
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args = f._arg_cls.parse(self.read_buf(p_arg, size))
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ret = f(fd, args)
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elif ioctl.DIR & _IOC_READ:
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args = f._arg_cls.parse(bytes(size))
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ret = f(fd, args)
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else:
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ret = f(fd)
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if ioctl.DIR & _IOC_READ:
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data = args.build()
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assert len(data) == size
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ctypes.memmove(p_arg, data, size)
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return ret
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Shim = DRMAsahiShim
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