mirror of
https://github.com/AsahiLinux/m1n1
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dart-t8110: Initial commit
Signed-off-by: R <rqou@berkeley.edu>
This commit is contained in:
R
Hector Martin
parent
0ba2027e5e
commit
4a09eca74a
3 changed files with 515 additions and 0 deletions
21
proxyclient/hv/trace_dart8110.py
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21
proxyclient/hv/trace_dart8110.py
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@ -0,0 +1,21 @@
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# SPDX-License-Identifier: MIT
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from m1n1.trace.dart8110 import DART8110Tracer
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DART8110Tracer = DART8110Tracer._reloadcls()
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DEVICES = [
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"/arm-io/dart-apr0",
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"/arm-io/dart-apr1",
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]
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dart_tracers = {}
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for i in DEVICES:
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p.pmgr_adt_clocks_enable(i)
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tracer = DART8110Tracer(hv, i, verbose=3)
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tracer.start()
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dart_tracers[i.split("-")[-1]] = tracer
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del tracer
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448
proxyclient/m1n1/hw/dart8110.py
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448
proxyclient/m1n1/hw/dart8110.py
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@ -0,0 +1,448 @@
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# SPDX-License-Identifier: MIT
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import struct
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from enum import IntEnum
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from ..utils import *
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from ..malloc import Heap
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__all__ = ["DART8110Regs", "DART8110"]
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class R_PARAMS_0(Register32):
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CLIENT_PARTITIONS_SUPPORTED = 29
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LOG2_PGSZ = 27, 24
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LOG2_TE_COUNT = 22, 20
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TLB_SET_COUNT = 11, 0
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class R_PARAMS_4(Register32):
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LOG2_NUM_WAYS = 30, 28
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NUM_ASCS = 25, 24
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NUM_W_PORTS = 22, 20
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NUM_R_PORTS = 18, 16
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NUM_APFS = 15, 8
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SUPPORT_STT_PREFETCH = 6
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SUPPORT_TLB_PREFETCH = 5
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SUPPORT_CTC_PREFETCH = 4
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SUPPORT_HW_FLUSH = 3
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SUPPORT_TZ_TAGGER = 2
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SUPPORT_REG_LOCK = 1
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SUPPORT_FULL_BYPASS = 0
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class R_PARAMS_8(Register32):
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PA_WIDTH = 29, 24
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VA_WIDTH = 21, 16
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VERS_MAJ = 15, 8
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VERS_MIN = 7, 0
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class R_PARAMS_C(Register32):
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NUM_CLIENTS = 24, 16
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NUM_SIDS = 8, 0
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# class R_ERROR(Register32):
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# FLAG = 31
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# STREAM = 27, 24
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# CODE = 23, 0
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# NO_DAPF_MATCH = 11
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# WRITE = 10
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# SUBPAGE_PROT = 7
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# PTE_READ_FAULT = 6
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# READ_FAULT = 4
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# WRITE_FAULT = 3
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# NO_PTE = 2
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# NO_PMD = 1
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# NO_TTBR = 0
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class R_TLB_OP(Register32):
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BUSY = 31
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# there are more bits here that may not be supported on hwrev 1
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# 0 = flush all
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# 1 = flush SID
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# 2 = TLB read
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# 3 = TLB write????
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OP = 10, 8
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STREAM = 7, 0
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class R_TCR(Register32):
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REMAP = 11, 8
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REMAP_EN = 7
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FOUR_LEVELS = 3 # not supported on hwrev 1
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BYPASS_DAPF = 2
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BYPASS_DART = 1
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TRANSLATE_ENABLE = 0
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class R_TTBR(Register32):
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ADDR = 29, 2
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VALID = 0
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class PTE(Register64):
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SP_START = 63, 52
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SP_END = 51, 40
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OFFSET = 37, 10
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RDPROT = 3
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WRPROT = 2
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UNCACHABLE = 1
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VALID = 0
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class DART8110Regs(RegMap):
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PARAMS_0 = 0x000, R_PARAMS_0
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PARAMS_4 = 0x004, R_PARAMS_4
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PARAMS_8 = 0x008, R_PARAMS_8
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PARAMS_C = 0x00C, R_PARAMS_C
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TLB_OP = 0x080, R_TLB_OP
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# ERROR = 0x40, R_ERROR
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# ERROR_ADDR_LO = 0x50, Register32
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# ERROR_ADDR_HI = 0x54, Register32
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ENABLE_STREAMS = irange(0xc00, 8, 4), Register32
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DISABLE_STREAMS = irange(0xc20, 8, 4), Register32
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TCR = irange(0x1000, 256, 4), R_TCR
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TTBR = irange(0x1400, 256, 4), R_TTBR
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class DART8110(Reloadable):
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PAGE_BITS = 14
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PAGE_SIZE = 1 << PAGE_BITS
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L1_OFF = 25
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L2_OFF = 14
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IDX_BITS = 11
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Lx_SIZE = (1 << IDX_BITS)
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IDX_MASK = Lx_SIZE - 1
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def __init__(self, iface, regs, util=None, iova_range=(0x80000000, 0x90000000)):
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self.iface = iface
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self.regs = regs
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self.u = util
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self.pt_cache = {}
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enabled_streams = 0
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for i in range(8):
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enabled_streams |= regs.ENABLE_STREAMS[i].val << 32*i
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self.enabled_streams = enabled_streams
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self.iova_allocator = [Heap(iova_range[0], iova_range[1], self.PAGE_SIZE)
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for i in range(16)]
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@classmethod
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def from_adt(cls, u, path):
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dart_addr = u.adt[path].get_reg(0)[0]
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regs = DART8110Regs(u, dart_addr)
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dart = cls(u.iface, regs, u)
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return dart
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# def ioread(self, stream, base, size):
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# if size == 0:
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# return b""
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# ranges = self.iotranslate(stream, base, size)
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# iova = base
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# data = []
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# for addr, size in ranges:
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# if addr is None:
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# raise Exception(f"Unmapped page at iova {iova:#x}")
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# data.append(self.iface.readmem(addr, size))
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# iova += size
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# return b"".join(data)
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# def iowrite(self, stream, base, data):
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# if len(data) == 0:
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# return
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# ranges = self.iotranslate(stream, base, len(data))
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# iova = base
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# p = 0
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# for addr, size in ranges:
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# if addr is None:
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# raise Exception(f"Unmapped page at iova {iova:#x}")
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# self.iface.writemem(addr, data[p:p + size])
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# p += size
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# iova += size
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# def iomap(self, stream, addr, size):
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# iova = self.iova_allocator[stream].malloc(size)
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# self.iomap_at(stream, iova, addr, size)
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# return iova
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# def iomap_at(self, stream, iova, addr, size):
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# if size == 0:
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# return
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# if not (self.enabled_streams & (1 << stream)):
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# self.enabled_streams |= (1 << stream)
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# self.regs.ENABLED_STREAMS.val |= self.enabled_streams
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# tcr = self.regs.TCR[stream].reg
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# if tcr.BYPASS_DART and not tcr.TRANSLATE_ENABLE:
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# raise Exception("Stream is bypassed in DART")
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# if tcr.BYPASS_DART or not tcr.TRANSLATE_ENABLE:
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# raise Exception(f"Unknown DART mode {tcr}")
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# if addr & (self.PAGE_SIZE - 1):
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# raise Exception(f"Unaligned PA {addr:#x}")
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# if iova & (self.PAGE_SIZE - 1):
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# raise Exception(f"Unaligned IOVA {iova:#x}")
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# start_page = align_down(iova, self.PAGE_SIZE)
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# end = iova + size
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# end_page = align_up(end, self.PAGE_SIZE)
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# dirty = set()
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# for page in range(start_page, end_page, self.PAGE_SIZE):
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# paddr = addr + page - start_page
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# l0 = page >> self.L0_OFF
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# assert l0 < self.L0_SIZE
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# ttbr = self.regs.TTBR[stream, l0].reg
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# if not ttbr.VALID:
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# l1addr = self.u.memalign(self.PAGE_SIZE, self.PAGE_SIZE)
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# self.pt_cache[l1addr] = [0] * self.Lx_SIZE
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# ttbr.VALID = 1
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# ttbr.ADDR = l1addr >> 12
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# self.regs.TTBR[stream, l0].reg = ttbr
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# cached, l1 = self.get_pt(ttbr.ADDR << 12)
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# l1idx = (page >> self.L1_OFF) & self.IDX_MASK
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# l1pte = self.ptecls(l1[l1idx])
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# if not l1pte.VALID:
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# l2addr = self.u.memalign(self.PAGE_SIZE, self.PAGE_SIZE)
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# self.pt_cache[l2addr] = [0] * self.Lx_SIZE
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# l1pte = self.ptecls(
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# OFFSET=l2addr >> self.PAGE_BITS, VALID=1, SP_PROT_DIS=1)
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# l1[l1idx] = l1pte.value
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# dirty.add(ttbr.ADDR << 12)
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# else:
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# l2addr = l1pte.OFFSET << self.PAGE_BITS
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# dirty.add(l1pte.OFFSET << self.PAGE_BITS)
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# cached, l2 = self.get_pt(l2addr)
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# l2idx = (page >> self.L2_OFF) & self.IDX_MASK
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# self.pt_cache[l2addr][l2idx] = self.ptecls(
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# SP_START=0, SP_END=0xfff,
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# OFFSET=paddr >> self.PAGE_BITS, VALID=1, SP_PROT_DIS=1).value
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# for page in dirty:
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# self.flush_pt(page)
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# def iotranslate(self, stream, start, size):
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# if size == 0:
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# return []
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# tcr = self.regs.TCR[stream].reg
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# if tcr.BYPASS_DART and not tcr.TRANSLATE_ENABLE:
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# return [(start, size)]
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# if tcr.BYPASS_DART or not tcr.TRANSLATE_ENABLE:
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# raise Exception(f"Unknown DART mode {tcr}")
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# start = start & 0xffffffff
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# start_page = align_down(start, self.PAGE_SIZE)
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# start_off = start - start_page
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# end = start + size
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# end_page = align_up(end, self.PAGE_SIZE)
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# end_size = end - (end_page - self.PAGE_SIZE)
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# pages = []
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# for page in range(start_page, end_page, self.PAGE_SIZE):
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# l0 = page >> self.L0_OFF
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# assert l0 < self.L0_SIZE
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# ttbr = self.regs.TTBR[stream, l0].reg
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# if not ttbr.VALID:
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# pages.append(None)
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# continue
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# cached, l1 = self.get_pt(ttbr.ADDR << 12)
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# l1pte = self.ptecls(l1[(page >> self.L1_OFF) & self.IDX_MASK])
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# if not l1pte.VALID and cached:
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# cached, l1 = self.get_pt(ttbr.ADDR << 12, uncached=True)
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# l1pte = self.ptecls(l1[(page >> self.L1_OFF) & self.IDX_MASK])
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# if not l1pte.VALID:
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# pages.append(None)
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# continue
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# cached, l2 = self.get_pt(l1pte.OFFSET << self.PAGE_BITS)
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# l2pte = self.ptecls(l2[(page >> self.L2_OFF) & self.IDX_MASK])
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# if not l2pte.VALID and cached:
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# cached, l2 = self.get_pt(l1pte.OFFSET << self.PAGE_BITS, uncached=True)
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# l2pte = self.ptecls(l2[(page >> self.L2_OFF) & self.IDX_MASK])
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# if not l2pte.VALID:
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# pages.append(None)
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# continue
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# pages.append(l2pte.OFFSET << self.PAGE_BITS)
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# ranges = []
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# for page in pages:
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# if not ranges:
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# ranges.append((page, self.PAGE_SIZE))
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# continue
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# laddr, lsize = ranges[-1]
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# if ((page is None and laddr is None) or
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# (page is not None and laddr == (page - lsize))):
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# ranges[-1] = laddr, lsize + self.PAGE_SIZE
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# else:
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# ranges.append((page, self.PAGE_SIZE))
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# ranges[-1] = (ranges[-1][0], ranges[-1][1] - self.PAGE_SIZE + end_size)
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# if start_off:
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# ranges[0] = (ranges[0][0] + start_off if ranges[0][0] else None,
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# ranges[0][1] - start_off)
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# return ranges
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# def get_pt(self, addr, uncached=False):
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# cached = True
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# if addr not in self.pt_cache or uncached:
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# cached = False
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# self.pt_cache[addr] = list(
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# struct.unpack(f"<{self.Lx_SIZE}Q", self.iface.readmem(addr, self.PAGE_SIZE)))
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# return cached, self.pt_cache[addr]
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# def flush_pt(self, addr):
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# assert addr in self.pt_cache
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# self.iface.writemem(addr, struct.pack(f"<{self.Lx_SIZE}Q", *self.pt_cache[addr]))
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# def initialize(self):
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# for i in range(15):
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# self.regs.TCR[i].reg = R_TCR(TRANSLATE_ENABLE=1)
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# self.regs.TCR[15].reg = R_TCR(BYPASS_DART=1)
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# for i in range(16):
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# for j in range(4):
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# self.regs.TTBR[i, j].reg = R_TTBR(VALID = 0)
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# self.regs.ERROR.val = 0xffffffff
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# self.regs.UNK1.val = 0
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# self.regs.ENABLED_STREAMS.val = 0
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# self.enabled_streams = 0
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# self.invalidate_streams()
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# def show_error(self):
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# if self.regs.ERROR.reg.FLAG:
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# print(f"ERROR: {self.regs.ERROR.reg!s}")
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# print(f"ADDR: {self.regs.ERROR_ADDR_HI.val:#x}:{self.regs.ERROR_ADDR_LO.val:#x}")
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# self.regs.ERROR.val = 0xffffffff
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# def invalidate_streams(self, streams=0xffffffff):
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# self.regs.STREAM_SELECT.val = streams
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# self.regs.STREAM_COMMAND.val = R_STREAM_COMMAND(INVALIDATE=1)
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# while self.regs.STREAM_COMMAND.reg.BUSY:
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# pass
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def invalidate_cache(self):
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self.pt_cache = {}
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# def dump_table2(self, base, l1_addr):
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# def print_block(base, pte, start, last):
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# pgcount = last - start
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# pte.OFFSET -= pgcount
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# print(" page (%4d): %08x ... %08x -> %016x [%d%d]" % (
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# start, base + start*0x4000, base + (start+1)*0x4000,
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# pte.OFFSET << self.PAGE_BITS, pte.SP_PROT_DIS, pte.VALID))
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# if start < last:
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# print(" ==> (%4d): ... %08x -> %016x size: %08x" % (
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# last, base + (last+1)*0x4000,
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# (pte.OFFSET + pgcount - 1) << self.PAGE_BITS, pgcount << self.PAGE_BITS))
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# cached, tbl = self.get_pt(l1_addr)
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# unmapped = False
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# start = 0
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# next_pte = self.ptecls(VALID=0)
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# for i, pte in enumerate(tbl):
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# pte = self.ptecls(pte)
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# if not pte.VALID:
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# if not unmapped:
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# if next_pte.VALID:
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# print_block(base, next_pte, start, i)
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# print(" ...")
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# unmapped = True
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# next_pte = pte
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# continue
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# unmapped = False
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# if int(pte) != int(next_pte):
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# if next_pte.VALID:
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# print_block(base, next_pte, start, i)
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# start = i
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# next_pte = pte
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# next_pte.OFFSET += 1
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# if next_pte.VALID:
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# print_block(base, next_pte, start, 2048)
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# def dump_table(self, base, l1_addr):
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# cached, tbl = self.get_pt(l1_addr)
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# unmapped = False
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# for i, pte in enumerate(tbl):
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# pte = self.ptecls(pte)
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# if not pte.VALID:
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# if not unmapped:
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# print(" ...")
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# unmapped = True
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# continue
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# unmapped = False
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# print(" table (%d): %08x ... %08x -> %016x [%d%d]" % (
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# i, base + i*0x2000000, base + (i+1)*0x2000000,
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# pte.OFFSET << self.PAGE_BITS, pte.SP_PROT_DIS, pte.VALID))
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# self.dump_table2(base + i*0x2000000, pte.OFFSET << self.PAGE_BITS)
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# def dump_ttbr(self, idx, ttbr):
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# if not ttbr.VALID:
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# return
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# l1_addr = (ttbr.ADDR) << 12
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# print(" TTBR%d: %09x" % (idx, l1_addr))
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# self.dump_table(0, l1_addr)
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def dump_device(self, idx):
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tcr = self.regs.TCR[idx].reg
|
||||
ttbr = self.regs.TTBR[idx]
|
||||
print(f"dev {idx:02x}: TCR={tcr!s} TTBR = {ttbr!s}")
|
||||
|
||||
if tcr.TRANSLATE_ENABLE and tcr.BYPASS_DART:
|
||||
print(" mode: INVALID")
|
||||
elif tcr.TRANSLATE_ENABLE:
|
||||
print(" mode: TRANSLATE")
|
||||
|
||||
# for idx, ttbr in enumerate(ttbrs):
|
||||
# self.dump_ttbr(idx, ttbr.reg)
|
||||
elif tcr.BYPASS_DART:
|
||||
print(" mode: BYPASS")
|
||||
else:
|
||||
print(" mode: UNKNOWN")
|
||||
|
||||
def dump_all(self):
|
||||
for i in range(16):
|
||||
self.dump_device(i)
|
||||
|
||||
def dump_params(self):
|
||||
print(self.regs.PARAMS_0.reg)
|
||||
print(self.regs.PARAMS_4.reg)
|
||||
print(self.regs.PARAMS_8.reg)
|
||||
print(self.regs.PARAMS_C.reg)
|
||||
46
proxyclient/m1n1/trace/dart8110.py
Normal file
46
proxyclient/m1n1/trace/dart8110.py
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
# SPDX-License-Identifier: MIT
|
||||
|
||||
from ..hw.dart8110 import *
|
||||
from ..hv import TraceMode
|
||||
from ..utils import *
|
||||
from . import ADTDevTracer
|
||||
|
||||
class DART8110Tracer(ADTDevTracer):
|
||||
RELOAD_DEPS = [DART8110]
|
||||
|
||||
DEFAULT_MODE = TraceMode.ASYNC
|
||||
|
||||
REGMAPS = [DART8110Regs]
|
||||
NAMES = ["regs"]
|
||||
|
||||
@classmethod
|
||||
def _reloadcls(cls):
|
||||
global DART8110
|
||||
DART8110 = DART8110._reloadcls()
|
||||
return super()._reloadcls()
|
||||
|
||||
def start(self):
|
||||
super().start()
|
||||
# prime cache
|
||||
for i in range(16):
|
||||
self.regs.TCR[i].val
|
||||
self.regs.TTBR[i].val
|
||||
|
||||
for _ in range(8):
|
||||
self.regs.ENABLE_STREAMS[0].val
|
||||
|
||||
self.dart = DART8110(self.hv.iface, self.regs)
|
||||
|
||||
|
||||
def w_TLB_OP(self, tlb_op):
|
||||
if tlb_op.OP == 0:
|
||||
self.log(f"Invalidate all")
|
||||
self.dart.invalidate_cache()
|
||||
elif tlb_op.OP == 1:
|
||||
self.log(f"Invalidate Stream: {tlb_op.STREAM}")
|
||||
self.dart.invalidate_cache()
|
||||
else:
|
||||
self.log(f"Unknown TLB op {tlb_op}")
|
||||
|
||||
def w_TTBR(self, ttbr, idx):
|
||||
self.dart.dump_all()
|
||||
Loading…
Add table
Reference in a new issue