mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-11-22 22:53:04 +00:00
m1n1: move SPI register to m1n1.hw
Signed-off-by: Janne Grunau <j@jannau.net>
This commit is contained in:
Janne Grunau
Hector Martin
parent
e90be797a8
commit
45824d2676
2 changed files with 154 additions and 146 deletions
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@ -5,152 +5,7 @@ from m1n1.setup import *
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from m1n1 import asm
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from m1n1.shell import run_shell
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from m1n1.gpiola import GPIOLogicAnalyzer
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class R_CTRL(Register32):
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RX_FIFO_RESET = 3
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TX_FIFO_RESET = 2
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RUN = 0
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class R_PIN(Register32):
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CS = 1
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KEEP_MOSI = 0
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class R_CONFIG(Register32):
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# impl: 002fb1e6
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IE_TX_COMPLETE = 21
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b19 = 19
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FIFO_THRESH = 18, 17
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# 0 = 8 bytes
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# 1 = 4 bytes
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# 2 = 1 byte
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# 3 = disabled
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WORD_SIZE = 16, 15
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# 0 = 8bit
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# 1 = 16bit
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# 2 = 32bit
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LSB_FIRST = 13
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b12 = 12
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IE_RX_THRESH = 8
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IE_RX_COMPLETE = 7
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MODE = 6, 5
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# 0 = polled
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# 1 = irq
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CPOL = 2
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CPHA = 1
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class R_STATUS(Register32):
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TX_COMPLETE = 22
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TXRX_THRESH = 1 # updated if MODE == 1
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RX_COMPLETE = 0
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class R_FIFO_STAT(Register32):
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LEVEL_RX = 31, 24
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RX_EMPTY = 20
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LEVEL_TX = 15, 8
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TX_FULL = 4
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class R_ISTATUS1(Register32):
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TX_XFER_DONE = 1
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RX_XFER_DONE = 0
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class R_ISTATUS2(Register32):
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TX_OVERFLOW = 17
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RX_UNDERRUN = 16
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TX_EMPTY = 9
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RX_FULL = 8
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TX_THRESH = 5
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RX_THRESH = 4
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class R_CLKDIV(Register32):
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DIVIDER = 10, 0 # SPI freq = CLK / (DIVIDER + 1)
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class R_INTER_DLY(Register32):
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DELAY = 15, 0
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# FIFO size: 16 bytes
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# backend FIFO: TX 2 bytes, RX 1 byte?
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class R_XFSTATUS(Register32):
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SR_FULL = 26
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SHIFTING = 20
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STATE = 17, 16
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UNK = 0
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class R_DIVSTATUS(Register32):
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COUNT2 = 31, 16
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COUNT1 = 15, 0
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class R_SHIFTCONFIG(Register32):
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OVERRIDE_CS = 24
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BITS = 21, 16
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RX_ENABLE = 11
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TX_ENABLE = 10
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CS_AS_DATA = 9
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AND_CLK_DATA = 8
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#? = 2 # needs to be 1 for RX to not break
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CS_ENABLE = 1
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CLK_ENABLE = 0
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class R_PINCONFIG(Register32):
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MOSI_INIT_VAL = 10
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CS_INIT_VAL = 9
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CLK_INIT_VAL = 8
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KEEP_MOSI = 2
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KEEP_CS = 1
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KEEP_CLK = 0
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class R_DELAY(Register32):
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DELAY = 31, 16
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MOSI_VAL = 12
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CS_VAL = 10
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SCK_VAL = 8
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SET_MOSI = 6
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SET_CS = 5
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SET_SCK = 4
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NO_INTERBYTE = 1
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ENABLE = 0
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class R_SCK_CONFIG(Register32):
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PERIOD = 31, 16
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PHASE1 = 9
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PHASE0 = 8
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RESET_TO_IDLE = 4
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class R_SCK_PHASES(Register32):
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PHASE1_START = 31, 16
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PHASE0_START = 15, 0
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class SPIRegs(RegMap):
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CTRL = 0x00, R_CTRL
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CONFIG = 0x04, R_CONFIG
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STATUS = 0x08, R_STATUS
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PIN = 0x0C, R_PIN
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TXDATA = 0x10, Register32
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RXDATA = 0x20, Register32
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CLKDIV = 0x30, R_CLKDIV
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RXCNT = 0x34, Register32
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INTER_DLY = 0x38, R_INTER_DLY
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TXCNT = 0x4C, Register32
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FIFO_STAT = 0x10C, R_FIFO_STAT
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IMASK1 = 0x130, R_ISTATUS1
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ISTATUS1 = 0x134, R_ISTATUS1
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IMASK2 = 0x138, R_ISTATUS2
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ISTATUS2 = 0x13c, R_ISTATUS2
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SHIFTCONFIG = 0x150, R_SHIFTCONFIG
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PINCONFIG = 0x154, R_PINCONFIG
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PRE_DLY = 0x160, R_DELAY
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SCK_CONFIG = 0x164, R_SCK_CONFIG
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POST_DLY = 0x168, R_DELAY
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SCK_PHASES = 0x180, R_SCK_PHASES
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UNK_PHASE = 0x18c, Register32 # probably MISO sample point
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XFSTATUS = 0x1c0, R_XFSTATUS
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DIVSTATUS = 0x1e0, R_DIVSTATUS
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from m1n1.hw.spi import *
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p.smp_start_secondaries()
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153
proxyclient/m1n1/hw/spi.py
Normal file
153
proxyclient/m1n1/hw/spi.py
Normal file
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@ -0,0 +1,153 @@
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# SPDX-License-Identifier: MIT
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import struct
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from ..utils import *
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__all__ = ["SPIRegs"]
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class R_CTRL(Register32):
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RX_FIFO_RESET = 3
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TX_FIFO_RESET = 2
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RUN = 0
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class R_PIN(Register32):
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CS = 1
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KEEP_MOSI = 0
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class R_CONFIG(Register32):
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# impl: 002fb1e6
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IE_TX_COMPLETE = 21
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b19 = 19
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FIFO_THRESH = 18, 17
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# 0 = 8 bytes
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# 1 = 4 bytes
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# 2 = 1 byte
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# 3 = disabled
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WORD_SIZE = 16, 15
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# 0 = 8bit
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# 1 = 16bit
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# 2 = 32bit
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LSB_FIRST = 13
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b12 = 12
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IE_RX_THRESH = 8
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IE_RX_COMPLETE = 7
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MODE = 6, 5
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# 0 = polled
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# 1 = irq
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CPOL = 2
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CPHA = 1
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class R_STATUS(Register32):
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TX_COMPLETE = 22
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TXRX_THRESH = 1 # updated if MODE == 1
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RX_COMPLETE = 0
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class R_FIFO_STAT(Register32):
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LEVEL_RX = 31, 24
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RX_EMPTY = 20
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LEVEL_TX = 15, 8
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TX_FULL = 4
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class R_ISTATUS1(Register32):
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TX_XFER_DONE = 1
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RX_XFER_DONE = 0
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class R_ISTATUS2(Register32):
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TX_OVERFLOW = 17
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RX_UNDERRUN = 16
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TX_EMPTY = 9
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RX_FULL = 8
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TX_THRESH = 5
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RX_THRESH = 4
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class R_CLKDIV(Register32):
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DIVIDER = 10, 0 # SPI freq = CLK / (DIVIDER + 1)
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class R_INTER_DLY(Register32):
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DELAY = 15, 0
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# FIFO size: 16 bytes
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# backend FIFO: TX 2 bytes, RX 1 byte?
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class R_XFSTATUS(Register32):
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SR_FULL = 26
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SHIFTING = 20
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STATE = 17, 16
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UNK = 0
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class R_DIVSTATUS(Register32):
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COUNT2 = 31, 16
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COUNT1 = 15, 0
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class R_SHIFTCONFIG(Register32):
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OVERRIDE_CS = 24
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BITS = 21, 16
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RX_ENABLE = 11
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TX_ENABLE = 10
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CS_AS_DATA = 9
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AND_CLK_DATA = 8
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#? = 2 # needs to be 1 for RX to not break
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CS_ENABLE = 1
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CLK_ENABLE = 0
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class R_PINCONFIG(Register32):
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MOSI_INIT_VAL = 10
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CS_INIT_VAL = 9
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CLK_INIT_VAL = 8
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KEEP_MOSI = 2
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KEEP_CS = 1
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KEEP_CLK = 0
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class R_DELAY(Register32):
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DELAY = 31, 16
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MOSI_VAL = 12
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CS_VAL = 10
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SCK_VAL = 8
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SET_MOSI = 6
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SET_CS = 5
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SET_SCK = 4
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NO_INTERBYTE = 1
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ENABLE = 0
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class R_SCK_CONFIG(Register32):
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PERIOD = 31, 16
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PHASE1 = 9
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PHASE0 = 8
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RESET_TO_IDLE = 4
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class R_SCK_PHASES(Register32):
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PHASE1_START = 31, 16
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PHASE0_START = 15, 0
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class SPIRegs(RegMap):
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CTRL = 0x00, R_CTRL
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CONFIG = 0x04, R_CONFIG
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STATUS = 0x08, R_STATUS
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PIN = 0x0C, R_PIN
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TXDATA = 0x10, Register32
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RXDATA = 0x20, Register32
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CLKDIV = 0x30, R_CLKDIV
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RXCNT = 0x34, Register32
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INTER_DLY = 0x38, R_INTER_DLY
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TXCNT = 0x4C, Register32
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FIFO_STAT = 0x10C, R_FIFO_STAT
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IMASK1 = 0x130, R_ISTATUS1
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ISTATUS1 = 0x134, R_ISTATUS1
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IMASK2 = 0x138, R_ISTATUS2
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ISTATUS2 = 0x13c, R_ISTATUS2
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SHIFTCONFIG = 0x150, R_SHIFTCONFIG
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PINCONFIG = 0x154, R_PINCONFIG
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PRE_DLY = 0x160, R_DELAY
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SCK_CONFIG = 0x164, R_SCK_CONFIG
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POST_DLY = 0x168, R_DELAY
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SCK_PHASES = 0x180, R_SCK_PHASES
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UNK_PHASE = 0x18c, Register32 # probably MISO sample point
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XFSTATUS = 0x1c0, R_XFSTATUS
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DIVSTATUS = 0x1e0, R_DIVSTATUS
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