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m1n1.hw.i2c: Rename registers to PASemi names, add all bit defs
This can serve as hardware documentation of the PASemi peripheral, in lieu of public docs. Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin
parent
0b9829e227
commit
430e8d2e8a
1 changed files with 131 additions and 33 deletions
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@ -1,33 +1,131 @@
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# SPDX-License-Identifier: MIT
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from ..utils import *
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from enum import IntEnum
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__all__ = ["I2C", "I2CRegs"]
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class R_FIFO_TX(Register32):
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READ = 10
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STOP = 9
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START = 8
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DATA = 7, 0
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class R_MTXFIFO(Register32):
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READ = 10 # Read (DATA=count)
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STOP = 9 # Issue START before
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START = 8 # Issue STOP after
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DATA = 7, 0 # Byte to send or count
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class R_FIFO_RX(Register32):
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EMPTY = 8
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DATA = 7, 0
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class R_MRXFIFO(Register32):
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EMPTY = 8 # FIFO empty
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DATA = 7, 0 # FIFO data
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class R_STATUS(Register32):
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XFER_READY = 27
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class R_MCNT(Register32):
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S_RXCNT = 31, 24 # Slave RX count
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S_TXCNT = 23, 16 # Slave TX count
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M_RXCNT = 15, 8 # Master RX count
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M_TXCNT = 7, 0 # Master TX count
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class R_CONTROL(Register32):
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ENABLE = 11
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CLEAR_RX = 10
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CLEAR_TX = 9
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CLOCK = 7, 0
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class E_MST(IntEnum):
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IDLE = 0
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FRD1 = 1
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FRD2 = 2
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COMMAND = 3
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START = 4
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WRITE = 5
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READ = 6
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ACK = 7
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STOP = 8
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BAD = 15
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class E_SST(IntEnum):
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IDLE = 0
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START = 1
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ST_ACK = 2
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DATA = 3
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ACK = 4
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class R_XFSTA(Register32):
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MST = 27, 24, E_MST # Master controller state
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SRD = 20 # Slave read in progress
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SWR = 19 # Slave write in progress
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SST = 18, 16, E_SST # Slave controller state
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XFIFO = 9, 8 # FIFO number for error
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XFCNT = 7, 0 # Number of bytes in current xfer
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class R_SADDR(Register32):
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DEB = 31 # Enable SDA/SCL read debug
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DIR = 30 # Direct (bitbang) mode
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ENS = 29 # Enable slave interface
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RST_STX = 28 # Reset slave TX FIFO
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RST_SRX = 27 # Reset master RX fifo (if ^ both, controller too)
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PEN = 26 # Promiscuous mode (slave)
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AAE = 25 # SALT/ALTMASK enable
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SAE = 24 # SADDR enable
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ALTMASK = 23, 16 # MASK for SALT bits
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SALT = 15, 8 # Alt slave address
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SADDR = 7, 0 # Slave address
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class R_SMSTA(Register32):
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XIP = 28 # Xaction in progress
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XEN = 27 # Xaction ended
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UJF = 26 # UnJam failure
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JMD = 25 # Jam ocurred
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JAM = 24 # Currently jammed
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MTO = 23 # Master timeout
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MTA = 22 # Master arb lost
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MTN = 21 # Master received NACK
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MRF = 20 # Master RX fifo full
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MRNE = 19 # Master RX fifo not empty
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MTF = 17 # Master TX fifo full
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MTE = 16 # Master RX fifo empty
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STO = 15 # Slave timeout
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STA = 14 # Slave arb lost
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STN = 13 # Slave received NACK
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SRF = 12 # Slave RX fifo full
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SRNE = 11 # Slave RX fifo not empty
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STR = 10 # Slave transmit required
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STF = 9 # Slave TX fifo full
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STE = 8 # Slave TX fifo empty
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TOS = 7 # Timeout due to slave FIFO
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TOM = 6 # Timeout due to master FIFO
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TOE = 5 # Slave timeout due to ext clock stretch
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DCI = 4 # Direct clock in
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DDI = 3 # Direct data in
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DCO = 2 # Direct clock out
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DDO = 1 # Direct data out
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NN = 0 # NACK next (slave)
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class R_CTL(Register32):
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MSW = 26, 16 # Maximum slave write size
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ENABLE = 11 # Unknown enable bit (clock sel? Apple thing)
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MRR = 10 # Master receive FIFO reset
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MTR = 9 # Master transmit FIFO reset
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UJM = 8 # Enable auto unjam machine
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CLK = 7, 0 # Clock divider
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class R_STXFIFO(Register32):
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DATA = 7, 0 # Data
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class R_SRXFIFO(Register32):
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N = 12 # NACK received after this byte
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P = 11 # Stop received, data not valid
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S = 10 # Start received before
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O = 9 # Overflow (promisc only)
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E = 8 # Empty (data not valid)
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DATA = 7, 0 # Data
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# Apple reg
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class R_FIFOCTL(Register32):
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HALT = 0 # Halt machinery
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class I2CRegs(RegMap):
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FIFO_TX = 0x00, R_FIFO_TX
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FIFO_RX = 0x04, R_FIFO_RX
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STATUS = 0x14, R_STATUS
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CONTROL = 0x1c, R_CONTROL
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MTXFIFO = 0x00, R_MTXFIFO
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MRXFIFO = 0x04, R_MRXFIFO
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MCNT = 0x08, R_MCNT
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XFSTA = 0x0c, R_XFSTA
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SADDR = 0x10, R_SADDR
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SMSTA = 0x14, R_SMSTA
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IMASK = 0x18, R_SMSTA
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CTL = 0x1c, R_CTL
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STXFIFO = 0x20, R_STXFIFO
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SRXFIFO = 0x20, R_SRXFIFO
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FIFOCTL = 0x44, R_FIFOCTL
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class I2C:
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@ -39,18 +137,18 @@ class I2C:
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self.regs = I2CRegs(u, self.base)
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def clear_fifos(self):
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self.regs.CONTROL.set(CLEAR_TX=1, CLEAR_RX=1)
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self.regs.CTL.set(MTR=1, MRR=1)
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def clear_status(self):
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self.regs.STATUS.val = 0xffffffff
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self.regs.SMSTA.val = 0xffffffff
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def _fifo_read(self, nbytes):
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read = []
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for _ in range(nbytes):
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val = self.regs.FIFO_RX.reg
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val = self.regs.MRXFIFO.reg
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timeout = 10000
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while val.EMPTY and timeout > 0:
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val = self.regs.FIFO_RX.reg
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val = self.regs.MRXFIFO.reg
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timeout -= 1
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if timeout == 0:
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raise Exception("timeout")
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@ -60,13 +158,13 @@ class I2C:
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def _fifo_write(self, buf, stop=False):
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for no, byte in enumerate(buf):
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sending_stop = stop and no == len(buf) - 1
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self.regs.FIFO_TX.set(DATA=byte, STOP=int(sending_stop))
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self.regs.MTXFIFO.set(DATA=byte, STOP=int(sending_stop))
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if not stop:
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return
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timeout = 10000
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while not self.regs.STATUS.reg.XFER_READY and timeout > 0:
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while not self.regs.SMSTA.reg.XEN and timeout > 0:
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timeout -= 1
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if timeout == 0:
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raise Exception("timeout")
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@ -75,20 +173,20 @@ class I2C:
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self.clear_fifos()
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self.clear_status()
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self.regs.CONTROL.set(ENABLE=1, CLOCK=0x4)
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self.regs.FIFO_TX.set(DATA=addr << 1, START=1)
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self.regs.CTL.set(ENABLE=1, CLK=0x4)
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self.regs.MTXFIFO.set(DATA=addr << 1, START=1)
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self._fifo_write(bytes([reg]) + bytes(data), stop=True)
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self.regs.CONTROL.set(ENABLE=0, CLOCK=0x4)
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self.regs.CTL.set(ENABLE=0, CLK=0x4)
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def read_reg(self, addr, reg, nbytes):
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self.clear_fifos()
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self.clear_status()
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self.regs.CONTROL.set(ENABLE=1, CLOCK=0x4)
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self.regs.FIFO_TX.set(DATA=addr << 1, START=1)
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self.regs.CTL.set(ENABLE=1, CLK=0x4)
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self.regs.MTXFIFO.set(DATA=addr << 1, START=1)
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self._fifo_write(bytes([reg]), stop=True)
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self.regs.FIFO_TX.set(DATA=(addr << 1) | 1, START=1)
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self.regs.FIFO_TX.set(DATA=nbytes, STOP=1, READ=1)
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self.regs.MTXFIFO.set(DATA=(addr << 1) | 1, START=1)
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self.regs.MTXFIFO.set(DATA=nbytes, STOP=1, READ=1)
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data = self._fifo_read(nbytes)
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self.regs.CONTROL.set(ENABLE=0, CLOCK=0x4)
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self.regs.CTL.set(ENABLE=0, CLK=0x4)
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return data
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