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hv.py: Be more selective about MMIO tracing

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Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin 2021-05-28 01:25:58 +09:00
parent fe651cb9d7
commit 3427bc0a2e
1 changed files with 36 additions and 20 deletions
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56
proxyclient/hv.py
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@ -565,32 +565,48 @@ class HV:
self.iface.set_handler(START.HV, HV_EVENT.WDT_BARK, self.handle_bark)
self.iface.set_event_handler(EVENT.MMIOTRACE, self.handle_mmiotrace)
self.map_sw(0x2_00000000,
0x2_00000000 | self.SPTE_TRACE_READ | self.SPTE_TRACE_WRITE,
0x5_00000000)
#self.map_sw(0x2_00000000,
#0x2_00000000 | self.SPTE_TRACE_READ | self.SPTE_TRACE_WRITE,
#0x5_00000000)
## Map UART directly so it doesn't spam
self.map_hw(0x2_35200000, 0x2_35200000, 0x4000)
self.map_hw(0x2_00000000, 0x2_00000000, 0x5_00000000)
## Map DWC directly so it doesn't spam
#self.map_hw(0x5_02280000, 0x5_02280000, 0x10000)
for path, log in (
("/arm-io/usb-drd0", False),
("/arm-io/usb-drd1", False),
("/arm-io/uart2", False),
("/arm-io/error-handler", False),
("/arm-io/aic", False),
("/arm-io/spi1", False),
("/arm-io/pmgr", False),
("/arm-io/gfx-asc", True),
("/arm-io/sgx", True),
):
node = self.adt[path]
for index in range(len(node.reg)):
addr, size = node.get_reg(index)
if addr & 0x3fff:
new_addr = addr & ~0x3fff
print(f"WARNING: aligning address 0x{addr:x} -> 0x{new_addr:x}")
size += addr - new_addr
addr = new_addr
# This also gets the syslog...
self.map_hw(0x2_3d12c000, 0x2_3d12c000, 0x4000)
if size & 0x3fff:
new_size = (size + 0x3fff) & ~0x3fff
print(f"WARNING: aligning size 0x{size:x} -> 0x{new_size:x}")
size = new_size
# SIMD loads lurk here...
self.map_hw(0x2_10e70000, 0x2_10e70000, 0x4000)
self.map_hw(0x2_11e70000, 0x2_11e70000, 0x4000)
self.map_hw(0x2_3e408000, 0x2_3e408000, 0x4000)
self.map_hw(0x2_3d2b8000, 0x2_3d2b8000, 0x4000)
# AIC Timer is noisy
self.map_hw(0x2_3b108000, 0x2_3b108000, 0x4000)
if log:
print(f"Trace: 0x{addr:x} [0x{size:x}] ({path})")
self.map_sw(addr, addr | self.SPTE_TRACE_READ | self.SPTE_TRACE_WRITE, size)
else:
print(f"Pass: 0x{addr:x} [0x{size:x}] ({path})")
self.map_hw(addr, addr, size)
# Sync PMGR stuff
self.map_sw(0x2_3b700000,
0x2_3b700000 | self.SPTE_TRACE_READ | self.SPTE_TRACE_WRITE | self.SPTE_SYNC_TRACE,
0x8000)
#self.map_sw(0x2_3b700000,
#0x2_3b700000 | self.SPTE_TRACE_READ | self.SPTE_TRACE_WRITE | self.SPTE_SYNC_TRACE,
#0x8000)
_pmu = {}