From 2c5b202c99f700b6f65bba6e0dd4eb33e1db0a2d Mon Sep 17 00:00:00 2001 From: Sven Peter Date: Sat, 8 May 2021 14:54:07 +0200 Subject: [PATCH] sysreg: add support for Apple's custom sysregs Signed-off-by: Sven Peter --- proxyclient/sysreg.py | 7 +- tools/apple_regs.json | 375 +++++++++++++++++++++++++++++++++++++++ tools/gen_reg_include.py | 2 +- 3 files changed, 380 insertions(+), 4 deletions(-) create mode 100644 tools/apple_regs.json diff --git a/proxyclient/sysreg.py b/proxyclient/sysreg.py index 8968f130..e240d689 100644 --- a/proxyclient/sysreg.py +++ b/proxyclient/sysreg.py @@ -5,9 +5,10 @@ from enum import IntEnum from utils import Register64, Register32 def load_registers(): - data = json.load(open(os.path.join(os.path.dirname(__file__), "..", "tools", "arm_regs.json"))) - for reg in data: - yield reg["name"], tuple(reg["enc"]) + for fname in ["arm_regs.json", "apple_regs.json"]: + data = json.load(open(os.path.join(os.path.dirname(__file__), "..", "tools", fname))) + for reg in data: + yield reg["name"], tuple(reg["enc"]) sysreg_fwd = dict(load_registers()) sysreg_rev = {v: k for k, v in sysreg_fwd.items()} diff --git a/tools/apple_regs.json b/tools/apple_regs.json new file mode 100644 index 00000000..6af47e07 --- /dev/null +++ b/tools/apple_regs.json @@ -0,0 +1,375 @@ +[ + { + "index": 0, + "name": "SPRR_CONFIG_EL1", + "fullname": "SPRR Configuration Register (EL3)", + "enc": [ + 3, + 6, + 15, + 1, + 0 + ], + "fieldsets": [ + { + "fields": [ + { + "name": "EN", + "msb": 0, + "lsb": 0 + }, + { + "name": "LOCK_CONFIG", + "msb": 1, + "lsb": 1 + }, + { + "name": "LOCK_PERM_EL0", + "msb": 4, + "lsb": 4 + }, + { + "name": "LOCK_PERM_EL1", + "msb": 5, + "lsb": 5 + } + ] + } + ], + "width": 64 + }, + { + "index": 0, + "name": "GXF_CONFIG_EL1", + "fullname": "GXF Configuration Register (EL3)", + "enc": [ + 3, + 6, + 15, + 1, + 2 + ], + "fieldsets": [ + { + "fields": [ + { + "name": "EN", + "msb": 0, + "lsb": 0 + } + ] + } + ], + "width": 64 + }, + { + "index": 0, + "name": "GXF_STATUS", + "fullname": "GXF Status Register", + "enc": [ + 3, + 6, + 15, + 8, + 0 + ], + "fieldsets": [ + { + "fields": [ + { + "name": "GUARDED", + "msb": 0, + "lsb": 0 + } + ] + } + ], + "width": 64 + }, + { + "index": 0, + "name": "GXF_ABORT_EL1", + "fullname": "GXF Abort Vector Register (EL1)", + "enc": [ + 3, + 6, + 15, + 8, + 2 + ], + "width": 64 + }, + { + "index": 0, + "name": "GXF_ENTER_EL1", + "fullname": "GXF genter Entry Vector Register (EL1)", + "enc": [ + 3, + 6, + 15, + 8, + 1 + ], + "width": 64 + }, + { + "index": 0, + "name": "GXF_ABORT_EL12", + "fullname": "GXF Abort Vector Register (EL12)", + "enc": [ + 3, + 6, + 15, + 15, + 3 + ], + "width": 64 + }, + { + "index": 0, + "name": "GXF_ENTER_EL12", + "fullname": "GXF genter Entry Vector Register (EL12)", + "enc": [ + 3, + 6, + 15, + 15, + 2 + ], + "width": 64 + }, + { + "index": 0, + "name": "SPRR_PERM_EL0", + "fullname": "SPRR Permission Configuration Register (EL0)", + "enc": [ + 3, + 6, + 15, + 1, + 5 + ], + "width": 64 + }, + { + "index": 0, + "name": "SPRR_PERM_EL1", + "fullname": "SPRR Permission Configuration Register (EL1)", + "enc": [ + 3, + 6, + 15, + 1, + 6 + ], + "width": 64 + }, + { + "index": 0, + "name": "TPIDR_GL1", + "fullname": "Software Thread ID Register (GL1)", + "enc": [ + 3, + 6, + 15, + 10, + 1 + ], + "width": 64 + }, + { + "index": 0, + "name": "VBAR_GL1", + "fullname": "Vector Base Address Register (GL1)", + "enc": [ + 3, + 6, + 15, + 10, + 2 + ], + "width": 64 + }, + { + "index": 0, + "name": "SPSR_GL1", + "fullname": "Saved Program Status Register (GL1)", + "enc": [ + 3, + 6, + 15, + 10, + 3 + ], + "width": 64 + }, + { + "index": 0, + "name": "ASPSR_GL1", + "fullname": "ASPSR (GL1)", + "enc": [ + 3, + 6, + 15, + 10, + 4 + ], + "width": 64 + }, + { + "index": 0, + "name": "ESR_GL1", + "fullname": "Exception Syndrome Register (GL1)", + "enc": [ + 3, + 6, + 15, + 10, + 5 + ], + "width": 64 + }, + { + "index": 0, + "name": "ELR_GL1", + "fullname": "Exception Link Register (GL1)", + "enc": [ + 3, + 6, + 15, + 10, + 6 + ], + "width": 64 + }, + { + "index": 0, + "name": "FAR_GL1", + "fullname": "Fault Address Register (GL1)", + "enc": [ + 3, + 6, + 15, + 10, + 7 + ], + "width": 64 + }, + { + "index": 0, + "name": "TPIDR_GL2", + "fullname": "Software Thread ID Register (GL2)", + "enc": [ + 3, + 6, + 15, + 11, + 1 + ], + "width": 64 + }, + { + "index": 0, + "name": "VBAR_GL2", + "fullname": "Vector Base Address Register (GL2)", + "enc": [ + 3, + 6, + 15, + 11, + 2 + ], + "width": 64 + }, + { + "index": 0, + "name": "SPSR_GL2", + "fullname": "Saved Program Status Register (GL2)", + "enc": [ + 3, + 6, + 15, + 11, + 3 + ], + "width": 64 + }, + { + "index": 0, + "name": "ASPSR_GL2", + "fullname": "ASPSR (GL2)", + "enc": [ + 3, + 6, + 15, + 11, + 4 + ], + "width": 64 + }, + { + "index": 0, + "name": "ESR_GL2", + "fullname": "Exception Syndrome Register (GL2)", + "enc": [ + 3, + 6, + 15, + 11, + 5 + ], + "width": 64 + }, + { + "index": 0, + "name": "ELR_GL2", + "fullname": "Exception Link Register (GL2)", + "enc": [ + 3, + 6, + 15, + 11, + 6 + ], + "width": 64 + }, + { + "index": 0, + "name": "FAR_GL2", + "fullname": "Fault Address Register (GL2)", + "enc": [ + 3, + 6, + 15, + 11, + 7 + ], + "width": 64 + }, + { + "index": 0, + "name": "VBAR_GL12", + "fullname": "Vector Base Address Register (GL12)", + "enc": [ + 3, + 6, + 15, + 9, + 2 + ], + "width": 64 + }, + { + "index": 0, + "name": "SP_GL12", + "fullname": "Stack Pointer Register (GL12)", + "enc": [ + 3, + 6, + 15, + 10, + 0 + ], + "width": 64 + } +] diff --git a/tools/gen_reg_include.py b/tools/gen_reg_include.py index d7f49367..ff751ad8 100644 --- a/tools/gen_reg_include.py +++ b/tools/gen_reg_include.py @@ -9,7 +9,7 @@ for reg in data: if name[-4:-1] == "_EL": name = name[:-4] - for fieldset in reg["fieldsets"]: + for fieldset in reg.get("fieldsets", []): if "instance" in fieldset: print(f"// {fieldset['instance']}") for f in fieldset["fields"]: