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https://github.com/AsahiLinux/m1n1
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dart-t8110: map/translate
Signed-off-by: R <rqou@berkeley.edu>
This commit is contained in:
R
Hector Martin
parent
5b07956e43
commit
25ebf8adb1
1 changed files with 102 additions and 105 deletions
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@ -170,140 +170,137 @@ class DART8110(Reloadable):
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# self.iomap_at(stream, iova, addr, size)
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# return iova
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# def iomap_at(self, stream, iova, addr, size):
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# if size == 0:
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# return
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def iomap_at(self, stream, iova, addr, size):
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if size == 0:
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return
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# if not (self.enabled_streams & (1 << stream)):
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# self.enabled_streams |= (1 << stream)
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# self.regs.ENABLED_STREAMS.val |= self.enabled_streams
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if not (self.enabled_streams & (1 << stream)):
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self.enabled_streams |= (1 << stream)
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self.regs.ENABLE_STREAMS[stream // 32].val |= (1 << (stream % 32))
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# tcr = self.regs.TCR[stream].reg
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tcr = self.regs.TCR[stream].reg
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# if tcr.BYPASS_DART and not tcr.TRANSLATE_ENABLE:
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# raise Exception("Stream is bypassed in DART")
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if tcr.BYPASS_DART and not tcr.TRANSLATE_ENABLE:
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raise Exception("Stream is bypassed in DART")
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# if tcr.BYPASS_DART or not tcr.TRANSLATE_ENABLE:
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# raise Exception(f"Unknown DART mode {tcr}")
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if tcr.BYPASS_DART or not tcr.TRANSLATE_ENABLE:
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raise Exception(f"Unknown DART mode {tcr}")
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# if addr & (self.PAGE_SIZE - 1):
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# raise Exception(f"Unaligned PA {addr:#x}")
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if addr & (self.PAGE_SIZE - 1):
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raise Exception(f"Unaligned PA {addr:#x}")
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# if iova & (self.PAGE_SIZE - 1):
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# raise Exception(f"Unaligned IOVA {iova:#x}")
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if iova & (self.PAGE_SIZE - 1):
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raise Exception(f"Unaligned IOVA {iova:#x}")
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# start_page = align_down(iova, self.PAGE_SIZE)
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# end = iova + size
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# end_page = align_up(end, self.PAGE_SIZE)
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start_page = align_down(iova, self.PAGE_SIZE)
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end = iova + size
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end_page = align_up(end, self.PAGE_SIZE)
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# dirty = set()
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dirty = set()
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# for page in range(start_page, end_page, self.PAGE_SIZE):
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# paddr = addr + page - start_page
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for page in range(start_page, end_page, self.PAGE_SIZE):
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paddr = addr + page - start_page
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# l0 = page >> self.L0_OFF
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# assert l0 < self.L0_SIZE
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# ttbr = self.regs.TTBR[stream, l0].reg
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# if not ttbr.VALID:
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# l1addr = self.u.memalign(self.PAGE_SIZE, self.PAGE_SIZE)
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# self.pt_cache[l1addr] = [0] * self.Lx_SIZE
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# ttbr.VALID = 1
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# ttbr.ADDR = l1addr >> 12
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# self.regs.TTBR[stream, l0].reg = ttbr
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ttbr = self.regs.TTBR[stream].reg
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if not ttbr.VALID:
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l1addr = self.u.memalign(self.PAGE_SIZE, self.PAGE_SIZE)
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self.pt_cache[l1addr] = [0] * self.Lx_SIZE
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ttbr.VALID = 1
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ttbr.ADDR = l1addr >> self.PAGE_BITS
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self.regs.TTBR[stream].reg = ttbr
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# cached, l1 = self.get_pt(ttbr.ADDR << 12)
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# l1idx = (page >> self.L1_OFF) & self.IDX_MASK
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# l1pte = self.ptecls(l1[l1idx])
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# if not l1pte.VALID:
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# l2addr = self.u.memalign(self.PAGE_SIZE, self.PAGE_SIZE)
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# self.pt_cache[l2addr] = [0] * self.Lx_SIZE
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# l1pte = self.ptecls(
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# OFFSET=l2addr >> self.PAGE_BITS, VALID=1, SP_PROT_DIS=1)
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# l1[l1idx] = l1pte.value
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# dirty.add(ttbr.ADDR << 12)
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# else:
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# l2addr = l1pte.OFFSET << self.PAGE_BITS
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cached, l1 = self.get_pt(ttbr.ADDR << self.PAGE_BITS)
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l1idx = (page >> self.L1_OFF) & self.IDX_MASK
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l1pte = PTE(l1[l1idx])
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if not l1pte.VALID:
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l2addr = self.u.memalign(self.PAGE_SIZE, self.PAGE_SIZE)
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self.pt_cache[l2addr] = [0] * self.Lx_SIZE
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l1pte = PTE(
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OFFSET=l2addr >> self.PAGE_BITS, VALID=1)
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l1[l1idx] = l1pte.value
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dirty.add(ttbr.ADDR << self.PAGE_BITS)
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else:
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l2addr = l1pte.OFFSET << self.PAGE_BITS
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# dirty.add(l1pte.OFFSET << self.PAGE_BITS)
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# cached, l2 = self.get_pt(l2addr)
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# l2idx = (page >> self.L2_OFF) & self.IDX_MASK
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# self.pt_cache[l2addr][l2idx] = self.ptecls(
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# SP_START=0, SP_END=0xfff,
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# OFFSET=paddr >> self.PAGE_BITS, VALID=1, SP_PROT_DIS=1).value
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dirty.add(l1pte.OFFSET << self.PAGE_BITS)
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cached, l2 = self.get_pt(l2addr)
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l2idx = (page >> self.L2_OFF) & self.IDX_MASK
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self.pt_cache[l2addr][l2idx] = PTE(
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SP_START=0, SP_END=0xfff,
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OFFSET=paddr >> self.PAGE_BITS, VALID=1).value
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# for page in dirty:
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# self.flush_pt(page)
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for page in dirty:
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self.flush_pt(page)
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# def iotranslate(self, stream, start, size):
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# if size == 0:
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# return []
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def iotranslate(self, stream, start, size):
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if size == 0:
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return []
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# tcr = self.regs.TCR[stream].reg
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tcr = self.regs.TCR[stream].reg
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# if tcr.BYPASS_DART and not tcr.TRANSLATE_ENABLE:
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# return [(start, size)]
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if tcr.BYPASS_DART and not tcr.TRANSLATE_ENABLE:
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# FIXME this may not be correct
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return [(start, size)]
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# if tcr.BYPASS_DART or not tcr.TRANSLATE_ENABLE:
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# raise Exception(f"Unknown DART mode {tcr}")
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if tcr.BYPASS_DART or not tcr.TRANSLATE_ENABLE:
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raise Exception(f"Unknown DART mode {tcr}")
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# start = start & 0xffffffff
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start = start & 0xfffffffff
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# start_page = align_down(start, self.PAGE_SIZE)
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# start_off = start - start_page
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# end = start + size
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# end_page = align_up(end, self.PAGE_SIZE)
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# end_size = end - (end_page - self.PAGE_SIZE)
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start_page = align_down(start, self.PAGE_SIZE)
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start_off = start - start_page
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end = start + size
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end_page = align_up(end, self.PAGE_SIZE)
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end_size = end - (end_page - self.PAGE_SIZE)
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# pages = []
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pages = []
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# for page in range(start_page, end_page, self.PAGE_SIZE):
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# l0 = page >> self.L0_OFF
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# assert l0 < self.L0_SIZE
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# ttbr = self.regs.TTBR[stream, l0].reg
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# if not ttbr.VALID:
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# pages.append(None)
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# continue
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for page in range(start_page, end_page, self.PAGE_SIZE):
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ttbr = self.regs.TTBR[stream].reg
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if not ttbr.VALID:
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pages.append(None)
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continue
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# cached, l1 = self.get_pt(ttbr.ADDR << 12)
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# l1pte = self.ptecls(l1[(page >> self.L1_OFF) & self.IDX_MASK])
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# if not l1pte.VALID and cached:
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# cached, l1 = self.get_pt(ttbr.ADDR << 12, uncached=True)
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# l1pte = self.ptecls(l1[(page >> self.L1_OFF) & self.IDX_MASK])
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# if not l1pte.VALID:
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# pages.append(None)
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# continue
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cached, l1 = self.get_pt(ttbr.ADDR << self.PAGE_BITS)
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l1pte = PTE(l1[(page >> self.L1_OFF) & self.IDX_MASK])
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if not l1pte.VALID and cached:
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cached, l1 = self.get_pt(ttbr.ADDR << self.PAGE_BITS, uncached=True)
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l1pte = PTE(l1[(page >> self.L1_OFF) & self.IDX_MASK])
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if not l1pte.VALID:
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pages.append(None)
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continue
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# cached, l2 = self.get_pt(l1pte.OFFSET << self.PAGE_BITS)
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# l2pte = self.ptecls(l2[(page >> self.L2_OFF) & self.IDX_MASK])
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# if not l2pte.VALID and cached:
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# cached, l2 = self.get_pt(l1pte.OFFSET << self.PAGE_BITS, uncached=True)
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# l2pte = self.ptecls(l2[(page >> self.L2_OFF) & self.IDX_MASK])
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# if not l2pte.VALID:
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# pages.append(None)
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# continue
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cached, l2 = self.get_pt(l1pte.OFFSET << self.PAGE_BITS)
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l2pte = PTE(l2[(page >> self.L2_OFF) & self.IDX_MASK])
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if not l2pte.VALID and cached:
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cached, l2 = self.get_pt(l1pte.OFFSET << self.PAGE_BITS, uncached=True)
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l2pte = PTE(l2[(page >> self.L2_OFF) & self.IDX_MASK])
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if not l2pte.VALID:
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pages.append(None)
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continue
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# pages.append(l2pte.OFFSET << self.PAGE_BITS)
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pages.append(l2pte.OFFSET << self.PAGE_BITS)
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# ranges = []
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ranges = []
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# for page in pages:
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# if not ranges:
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# ranges.append((page, self.PAGE_SIZE))
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# continue
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# laddr, lsize = ranges[-1]
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# if ((page is None and laddr is None) or
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# (page is not None and laddr == (page - lsize))):
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# ranges[-1] = laddr, lsize + self.PAGE_SIZE
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# else:
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# ranges.append((page, self.PAGE_SIZE))
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for page in pages:
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if not ranges:
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ranges.append((page, self.PAGE_SIZE))
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continue
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laddr, lsize = ranges[-1]
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if ((page is None and laddr is None) or
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(page is not None and laddr == (page - lsize))):
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ranges[-1] = laddr, lsize + self.PAGE_SIZE
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else:
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ranges.append((page, self.PAGE_SIZE))
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# ranges[-1] = (ranges[-1][0], ranges[-1][1] - self.PAGE_SIZE + end_size)
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ranges[-1] = (ranges[-1][0], ranges[-1][1] - self.PAGE_SIZE + end_size)
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# if start_off:
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# ranges[0] = (ranges[0][0] + start_off if ranges[0][0] else None,
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# ranges[0][1] - start_off)
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if start_off:
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ranges[0] = (ranges[0][0] + start_off if ranges[0][0] else None,
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ranges[0][1] - start_off)
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# return ranges
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return ranges
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def get_pt(self, addr, uncached=False):
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cached = True
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