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hv_vm: Implement more opcodes

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Signed-off-by: Asahi Lina <lina@asahilina.net>
This commit is contained in:
Asahi Lina 2022-05-21 03:00:33 +09:00
parent 88c443008f
commit 25d33aa4c7
1 changed files with 18 additions and 0 deletions
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18
src/hv_vm.c
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@ -578,6 +578,15 @@ static bool emulate_load(struct exc_info *ctx, u32 insn, u64 *val, u64 *width, u
u64 Rt2 = (insn >> 10) & 0x1f;
regs[Rt] = val[0];
regs[Rt2] = val[1];
} else if ((insn & 0xfec00000) == 0xa8c00000) {
// LDP (pre/post-increment, 64-bit)
*width = 4;
*vaddr = regs[Rn] + ((insn & BIT(24)) ? (imm7 * 8) : 0);
DECODE_OK;
regs[Rn] += imm7 * 8;
u64 Rt2 = (insn >> 10) & 0x1f;
regs[Rt] = val[0];
regs[Rt2] = val[1];
} else if ((insn & 0xfec00000) == 0xac400000) {
// LD[N]P (SIMD&FP, 128-bit) Signed offset
*width = 5;
@ -698,6 +707,15 @@ static bool emulate_store(struct exc_info *ctx, u32 insn, u64 *val, u64 *width,
val[0] = regs[Rt];
val[1] = regs[Rt2];
*width = 4;
} else if ((insn & 0xfec00000) == 0xa8800000) {
// ST[N]P (immediate, 64-bit, pre/post-index)
CHECK_RN;
*vaddr = regs[Rn] + ((insn & BIT(24)) ? (imm7 * 8) : 0);
regs[Rn] += (imm7 * 8);
u64 Rt2 = (insn >> 10) & 0x1f;
val[0] = regs[Rt];
val[1] = regs[Rt2];
*width = 4;
} else if ((insn & 0x3fc00000) == 0x3d000000) {
// STR (immediate, SIMD&FP) Unsigned offset, 8..64-bit
get_simd_state(simd);