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chickens: Add T8112 chickens

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Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin 2022-06-27 18:15:38 +09:00
parent b16a19715a
commit 22adc922f7
4 changed files with 82 additions and 0 deletions
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2
Makefile
View file

@ -75,6 +75,8 @@ OBJECTS := \
chainload.o \
chainload_asm.o \
chickens.o \
chickens_avalanche.o \
chickens_blizzard.o \
chickens_firestorm.o \
chickens_icestorm.o \
clk.o \

17
src/chickens.c
View file

@ -14,6 +14,10 @@
#define MIDR_PART_T6000_FIRESTORM 0x25
#define MIDR_PART_T6001_ICESTORM 0x28
#define MIDR_PART_T6001_FIRESTORM 0x29
#define MIDR_PART_T8110_BLIZZARD 0x30
#define MIDR_PART_T8110_AVALANCHE 0x31
#define MIDR_PART_T8112_BLIZZARD 0x32
#define MIDR_PART_T8112_AVALANCHE 0x33
#define MIDR_REV_LOW GENMASK(3, 0)
#define MIDR_PART GENMASK(15, 4)
@ -24,6 +28,9 @@ void init_t8103_firestorm(int rev);
void init_t6000_firestorm(int rev);
void init_t6001_firestorm(int rev);
void init_m2_blizzard(void);
void init_t8112_avalanche(int rev);
const char *init_cpu(void)
{
const char *cpu = "Unknown";
@ -73,6 +80,16 @@ const char *init_cpu(void)
init_m1_icestorm();
break;
case MIDR_PART_T8112_AVALANCHE:
cpu = "M2 Avalanche";
init_t8112_avalanche(rev);
break;
case MIDR_PART_T8112_BLIZZARD:
cpu = "M2 Blizzard";
init_m2_blizzard();
break;
default:
uart_puts(" Unknown CPU type");
break;

45
src/chickens_avalanche.c Normal file
View file

@ -0,0 +1,45 @@
/* SPDX-License-Identifier: MIT */
#include "cpu_regs.h"
#include "utils.h"
static void init_common_avalanche(void)
{
reg_mask(SYS_IMP_APL_HID1, HID1_AVL_UNK42_MASK, HID1_AVL_UNK42(1));
reg_mask(SYS_IMP_APL_HID1, HID1_AVL_UNK22_MASK, HID1_AVL_UNK22(3));
reg_set(SYS_IMP_APL_HID9, HID9_TSO_ALLOW_DC_ZVA_WC | HID9_AVL_UNK17);
// "configure dummy cycles to work around incorrect temp sensor readings on
// NEX power gating" (maybe)
reg_mask(SYS_IMP_APL_HID13,
HID13_AVL_UNK0_MASK | HID13_AVL_UNK7_MASK | HID13_PRE_CYCLES_MASK |
HID13_AVL_UNK26_MASK | HID13_AVL_UNK30_MASK | HID13_AVL_UNK34_MASK |
HID13_AVL_UNK38_MASK | HID13_AVL_UNK42_MASK | HID13_AVL_UNK46_MASK |
HID13_AVL_UNK50_MASK | HID13_RESET_CYCLE_COUNT_MASK,
HID13_AVL_UNK0(8) | HID13_AVL_UNK7(8) | HID13_PRE_CYCLES(1) | HID13_AVL_UNK26(4) |
HID13_AVL_UNK30(4) | HID13_AVL_UNK34(4) | HID13_AVL_UNK38(4) | HID13_AVL_UNK42(4) |
HID13_AVL_UNK46(4) | HID13_AVL_UNK50(4) | HID13_RESET_CYCLE_COUNT(0));
// No idea what the correct name for these registers is
reg_mask(s3_0_c15_c0_3, GENMASK(7, 0) | GENMASK(43, 36), (0x1aULL << 0) | (0x1fULL << 36));
reg_mask(s3_0_c15_c0_4, GENMASK(15, 8), (0x1fULL << 8));
}
static void init_m2_avalanche(void)
{
init_common_avalanche();
reg_mask(SYS_IMP_APL_HID3, HID3_AVL_UNK57_MASK, HID3_AVL_UNK57(0x3c));
reg_set(SYS_IMP_APL_HID3, HID3_DEV_PCIE_THROTTLE_ENABLE);
reg_set(SYS_IMP_APL_HID18, HID18_AVL_UNK27 | HID18_AVL_UNK29);
reg_set(SYS_IMP_APL_HID16, HID16_AVL_UNK12);
}
void init_t8112_avalanche(int rev)
{
UNUSED(rev);
init_m2_avalanche();
}

18
src/chickens_blizzard.c Normal file
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@ -0,0 +1,18 @@
/* SPDX-License-Identifier: MIT */
#include "cpu_regs.h"
#include "utils.h"
static void init_common_blizzard(void)
{
reg_set(SYS_IMP_APL_EHID0, EHID0_BLI_UNK32);
}
void init_m2_blizzard(void)
{
init_common_blizzard();
reg_mask(SYS_IMP_APL_EHID9, EHID9_BLZ_UNK6_MASK, EHID9_BLZ_UNK6(0x3c));
reg_set(SYS_IMP_APL_EHID9, EHID9_DEV_THROTTLE_2_ENABLE);
reg_set(SYS_IMP_APL_EHID18, EHID18_BLZ_UNK34);
}