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aic_test.py: more experiments

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Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin 2021-02-05 01:09:47 +09:00
parent 60665a2ee2
commit 19f915b779
1 changed files with 111 additions and 9 deletions
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120
proxyclient/aic_test.py
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@ -8,6 +8,10 @@ UFCON = 0x235200008
UTRSTAT = 0x235200010
AIC = 0x23b100000
AIC_RST = AIC + 0xc
AIC_CFG = AIC + 0x10
AIC_TB = 0x23b108000
AIC_TGT_DST = AIC + 0x3000
AIC_SW_GEN_SET = AIC + 0x4000
@ -36,18 +40,44 @@ def cpoll():
mon.poll()
print(">")
p.write32(AIC + 0xc, 1)
p.write32(AIC + 0x10, 0xe0777971)
p.write32(AIC + 0x18, 0)
p.write32(AIC + 0x20, 0xffffffff)
p.write32(AIC + 0x24, 0xffffffff)
p.write32(AIC + 0x28, 0xffffffff)
p.write32(AIC + 0x2c, 0xffffffff)
p.write32(AIC + 0x30, 0xffffffff)
p.write32(AIC + 0x34, 0xffffffff)
p.write32(AIC + 0x38, 0xffffffff)
p.write32(AIC + 0x3c, 0xffffffff)
p.write32(AIC + 0x40, 0xffffffff)
p.write32(AIC + 0x38, 0xffffffff)
#p.write32(AIC + 0xc, 0)
p.memset32(AIC_MASK_SET, 0xffffffff, 0x80)
p.memset32(AIC_SW_GEN_CLR, 0xffffffff, 0x80)
p.memset32(AIC_TGT_DST, 1, 0x1000)
p.memset32(AIC_TGT_DST, 0x1, 0x1000)
#p.memset32(AIC_MASK_CLR, 0xffffffff, 0x80)
#mon.add(AIC + 0x0000, 0x100)
#mon.add(AIC + 0x1000, 0x100)
#mon.add(AIC + 0x2008, 0x0f8)
#p.write32(AIC + 0x10, 0xe0777971)
mon.add(AIC + 0x0000, 0x1000)
mon.add(AIC + 0x2080, 0x040)
mon.add(AIC + 0x4000, 0x200)
mon.add(AIC + 0x5000, 0x080)
mon.add(AIC + 0x5080, 0x080)
mon.add(AIC + 0x5100, 0x080)
mon.add(AIC + 0x5180, 0x080)
mon.add(AIC + 0x5200, 0x080)
mon.add(AIC + 0x5280, 0x080)
mon.add(AIC + 0x5300, 0x080)
mon.add(AIC + 0x5380, 0x080)
#mon.add(AIC + 0x3000, 0x400)
#mon.add(AIC + 0x4000, 0x400)
#mon.add(AIC + 0x8000, 0x20)
#mon.add(AIC + 0x8030, 0xd0)
mon.add(0x235200000, 0x20)
#mon.add(0x235200000, 0x20)
def test_ipi():
cpoll()
@ -105,9 +135,18 @@ def test_timer():
freq = u.mrs(CNTFRQ_EL0)
print("Timer freq: %d" % freq)
u.msr(CNTP_CTL_EL0, 0)
u.msr(CNTP_TVAL_EL0, freq * 2)
u.msr(CNTP_CTL_EL0, 1)
#u.msr(CNTP_CTL_EL0, 0)
#u.msr(CNTP_TVAL_EL0, freq * 2)
#u.msr(CNTP_CTL_EL0, 1)
#u.msr(CNTV_CTL_EL0, 0)
#u.msr(CNTV_TVAL_EL0, freq * 2)
#u.msr(CNTV_CTL_EL0, 1)
#u.msr(CNTHV_CTL_EL2, 0)
#u.msr(CNTHV_TVAL_EL2, freq * 2)
#u.msr(CNTHV_CTL_EL2, 1)
u.msr(CNTHP_CTL_EL2, 0)
u.msr(CNTHP_TVAL_EL2, freq * 2)
u.msr(CNTHP_CTL_EL2, 1)
iface.ttymode()
@ -296,8 +335,71 @@ UCON UTRSTAT
def test_smp_ipi():
code = u.malloc(0x1000)
c = asm.ARMAsm("""
#define sys_reg(op0, op1, CRn, CRm, op2) s##op0##_##op1##_c##CRn##_c##CRm##_##op2
#define SYS_CYC_OVRD sys_reg(3, 5, 15, 5, 0)
msr DAIFClr, 7
ldr x1, =0x000000
msr SYS_CYC_OVRD, x1
mrs x0, SYS_CYC_OVRD
mov x1, #0x1000000
1:
subs x1, x1, #1
mrs x0, HCR_EL2
bne 1b
ret
""", code)
iface.writemem(code, c.data)
p.dc_cvau(code, len(c.data))
p.ic_ivau(code, len(c.data))
print("Enable IRQs on secondaries")
for i in range(1, 8):
ret = p.smp_call_sync(i, code)
print("0x%x"%ret)
#e0477971
#p.write32(AIC + 0x10, 0xe0777971)
#p.write32(AIC + 0x28, 0xffffffff)
cpoll()
print("Clear IPI")
p.write32(AIC_IPI_CLR, 0xffffffff)
p.write32(AIC_IPI_MASK_CLR, 0xffffffff)
for i in range(8):
p.write32(AIC_IPI_CLR+0x3000+i*0x80, 0xffffffff)
p.write32(AIC_IPI_MASK_CLR+0x3000+i*0x80, 0xffffffff)
cpoll()
print("Set IPI")
#p.write32(AIC_IPI_SET, 0x00000004)
#p.write32(AIC_IPI_SET, 0x00000000)
cpoll()
print("Clear IPI")
p.write32(AIC_IPI_CLR, 0xffffffff)
p.write32(AIC_IPI_MASK_CLR, 0xffffffff)
for i in range(8):
p.write32(AIC_IPI_CLR+0x3000+i*0x80, 1)
p.write32(AIC_IPI_MASK_CLR+0x3000+i*0x80, 1)
def test_smp_affinity():
p.write32(AIC_TGT_DST, 0x6)
p.write32(AIC_TGT_DST+4, 0xfe)
p.write32(AIC_TGT_DST+8, 0xfe)
p.write32(AIC_TGT_DST+12, 0x6)
p.write32(AIC_SW_GEN_SET,0x8);
p.write32(AIC_MASK_CLR,0x8);
#test_ipi()
#test_timer()
test_uart_irq()
#test_uart_irq()
test_smp_ipi()
test_smp_affinity()