m1n1.agx: Add FWCtl ring

Signed-off-by: Asahi Lina <lina@asahilina.net>
This commit is contained in:
Asahi Lina 2022-08-17 14:24:49 +09:00
parent 0aee8b7e2e
commit 1275e15b58

View file

@ -133,7 +133,10 @@ class AGX:
info = ChannelInfo()
info.state_addr = state_obj._addr
info.ringbuffer_addr = ring_buf._addr
setattr(self.ch_info, name, info)
if name == "FWCtl":
self.fwctl_chinfo = info
else:
setattr(self.ch_info, name, info)
return [cls(self, name + ("" if count == 1 else f"[{i}]"), channel_id,
state_obj._paddr + 0x30 * i,
@ -165,6 +168,8 @@ class AGX:
self.ch.ktrace = self.alloc_channels(GPUKTraceChannel, "KTrace", None, rx=True)[0]
self.ch.stats = self.alloc_channels(GPUStatsChannel, "Stats", None, rx=True)[0]
self.ch.fwctl = self.alloc_channels(GPUFWCtlChannel, "FWCtl", None, rx=False)[0]
# For some reason, the FWLog channels have their rings in a different place...
self.fwlog_ring = self.ch_info.FWLog.ringbuffer_addr
self.ch_info.FWLog.ringbuffer_addr = self.kshared.buf(0x150000, "FWLog_Dummy")