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https://github.com/AsahiLinux/m1n1
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m1n1.hw.uat: Add RegMap accessor
Signed-off-by: Asahi Lina <lina@asahilina.net>
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d7a4f30043
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0fcaf69728
1 changed files with 39 additions and 0 deletions
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@ -98,6 +98,38 @@ class Page_PTE(Register64):
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f"{MemoryAttr(self.AttrIndex).name}, {['Global', 'Local'][self.nG]}, " \
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f"Owner={['FW', 'OS'][self.OS]}, AF={self.AF}] ({self.value:#x})"
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class UatAccessor(Reloadable):
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def __init__(self, uat, ctx=0):
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self.uat = uat
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self.ctx = ctx
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def translate(self, addr, width):
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paddr, _ = self.uat.iotranslate(self.ctx, addr, width)[0]
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if paddr is None:
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raise Exception(f"UAT Failed to translate {addr:#x}")
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return paddr
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def read(self, addr, width):
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return self.uat.u.read(self.translate(addr, width), width)
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def read8(self, addr):
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return self.uat.p.read8(self.translate(addr, 1))
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def read16(self, addr):
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return self.uat.p.read16(self.translate(addr, 2))
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def read32(self, addr):
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return self.uat.p.read32(self.translate(addr, 4))
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def read64(self, addr):
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return self.uat.p.read64(self.translate(addr, 8))
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def write(self, addr, data, width):
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self.uat.u.write(self.translate(addr, width), data, width)
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def write8(self, addr, data):
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self.uat.p.write8(self.translate(addr, 1), daat)
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def write16(self, addr, data):
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self.uat.p.write6(self.translate(addr, 2), data)
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def write32(self, addr, data):
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self.uat.p.write32(self.translate(addr, 4), data)
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def write64(self, addr, data):
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self.uat.p.write64(self.translate(addr, 8), data)
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class UatStream(Reloadable):
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CACHE_SIZE = 0x1000
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@ -109,6 +141,9 @@ class UatStream(Reloadable):
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self.cache = None
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self.meta_fn = None
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def to_accessor(self):
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return UatAccessor(self.uat, self.ctx)
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def read(self, size):
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assert size >= 0
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@ -258,6 +293,10 @@ class UAT(Reloadable):
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def iostream(self, ctx, base):
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return UatStream(self, ctx, base)
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# A read/write register interface like proxy/utils objects that can be used by RegMap
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def ioaccessor(self, ctx, base):
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return UatAccessor(self, ctx)
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def iomap(self, ctx, addr, size, **flags):
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iova = self.allocator.malloc(size)
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