timer_test.py: More exhaustive tests

Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin 2021-04-14 17:46:14 +09:00
parent f30e91b933
commit 0df6db324b
2 changed files with 82 additions and 37 deletions

View file

@ -8,52 +8,94 @@ HV_VTMR_LIST = (3, 5, 15, 1, 2)
TGE = (1<<27)
def test_hv_timers():
u.msr(DAIF, 0)
print("Testing HV timers...")
u.msr(HCR_EL2, u.mrs(HCR_EL2) | TGE)
u.msr(CNTHCTL_EL2, 3 << 10) # EL1PTEN | EL1PCTEN
def run_test(ctl, tval):
u.inst(0xd5033fdf) # isb
u.msr(CNTHP_CTL_EL2, 0)
u.msr(CNTHP_TVAL_EL2, freq // 2)
u.msr(CNTHP_CTL_EL2, 1)
u.msr(CNTHV_CTL_EL2, 0)
u.msr(CNTHV_TVAL_EL2, freq * 1)
u.msr(CNTHV_CTL_EL2, 1)
u.msr(ctl, 0)
u.msr(tval, int(freq * 0.8))
u.msr(ctl, 1)
for i in range(6):
p.nop()
time.sleep(0.2)
print(". %x %x" % (u.mrs(CNTHP_CTL_EL2), u.mrs(CNTHV_CTL_EL2)))
#u.inst(0xd5033fdf, call=p.el1_call)
print(" . (ISR_EL1=%d) CTL=%x VTMR_LIST=%x" % (u.mrs(ISR_EL1), u.mrs(ctl), u.mrs(HV_VTMR_LIST)))
u.msr(ctl, 0)
def test_hv_timers():
u.msr(DAIF, 0x3c0)
print("Testing HV timers...")
print(" TGE = 1")
u.msr(HCR_EL2, u.mrs(HCR_EL2) | TGE | (1 << 3) | (1 << 4))
print(" P:")
run_test(CNTP_CTL_EL0, CNTP_TVAL_EL0)
print(" V:")
run_test(CNTV_CTL_EL0, CNTV_TVAL_EL0)
def test_guest_timers():
u.msr(DAIF, 0)
print("Testing guest timers...")
u.msr(HCR_EL2, (u.mrs(HCR_EL2) & (~TGE)) | (1 << 3) | (1 << 4))
print(" TGE = 1, vGIC mode=0, timers unmasked")
u.msr(HCR_EL2, (u.mrs(HCR_EL2) | TGE) | (1 << 3) | (1 << 4))
u.msr(HACR_EL2, 0)
u.msr(HV_VTMR_CTL, 3)
print(" P:")
#run_test(CNTP_CTL_EL02, CNTP_TVAL_EL02)
print(" V:")
#run_test(CNTV_CTL_EL02, CNTV_TVAL_EL02)
print(" TGE = 1, vGIC mode=0, timers masked")
u.msr(HV_VTMR_CTL, 0)
print(" P:")
run_test(CNTP_CTL_EL02, CNTP_TVAL_EL02)
print(" V:")
run_test(CNTV_CTL_EL02, CNTV_TVAL_EL02)
print(" TGE = 0, vGIC mode=0, timers unmasked")
u.msr(HCR_EL2, (u.mrs(HCR_EL2) & ~TGE) | (1 << 3) | (1 << 4))
u.msr(HACR_EL2, 0)
u.msr(HV_VTMR_CTL, 3)
print(" P:")
run_test(CNTP_CTL_EL02, CNTP_TVAL_EL02)
print(" V:")
run_test(CNTV_CTL_EL02, CNTV_TVAL_EL02)
print(" TGE = 0, vGIC mode=0, timers masked")
u.msr(HV_VTMR_CTL, 0)
print(" P:")
run_test(CNTP_CTL_EL02, CNTP_TVAL_EL02)
print(" V:")
run_test(CNTV_CTL_EL02, CNTV_TVAL_EL02)
print(" TGE = 0, vGIC mode=1, timers unmasked")
u.msr(HCR_EL2, (u.mrs(HCR_EL2) & ~TGE) | (1 << 3) | (1 << 4))
u.msr(HACR_EL2, 1<<20)
u.msr(HV_VTMR_CTL, 3)
u.inst(0xd5033fdf) # isb
print(" P:")
run_test(CNTP_CTL_EL02, CNTP_TVAL_EL02)
print(" V:")
run_test(CNTV_CTL_EL02, CNTV_TVAL_EL02)
u.msr(CNTP_CTL_EL02, 0)
u.msr(CNTP_TVAL_EL02, int(freq * 1))
print(" TGE = 0, vGIC mode=1, timers masked")
u.msr(HV_VTMR_CTL, 0)
u.msr(CNTV_CTL_EL02, 0)
u.msr(CNTV_TVAL_EL02, int(freq * 1.5))
print(" P:")
run_test(CNTP_CTL_EL02, CNTP_TVAL_EL02)
print(" V:")
run_test(CNTV_CTL_EL02, CNTV_TVAL_EL02)
u.msr(HV_VTMR_LIST, 0)
u.msr(CNTP_CTL_EL02, 1)
u.msr(CNTV_CTL_EL02, 1)
for i in range(15):
p.nop()
time.sleep(0.2)
print(". %x %x %x" % (u.mrs(CNTP_CTL_EL02), u.mrs(CNTV_CTL_EL02), u.mrs(HV_VTMR_LIST)))
return
freq = u.mrs(CNTFRQ_EL0)
print("Timer freq: %d" % freq)

View file

@ -272,16 +272,19 @@ void exc_fiq(u64 *regs)
msr(CNTV_CTL_EL0, 7L);
}
reg = mrs(CNTP_CTL_EL02);
if (reg == 0x5) {
uart_puts(" PHYS EL02 timer IRQ, masking");
msr(CNTP_CTL_EL02, 7L);
}
reg = mrs(CNTV_CTL_EL02);
if (reg == 0x5) {
uart_puts(" VIRT EL02 timer IRQ, masking");
msr(CNTV_CTL_EL02, 7L);
if (in_el2()) {
reg = mrs(CNTP_CTL_EL02);
if (reg == 0x5) {
uart_puts(" PHYS EL02 timer IRQ, masking");
msr(CNTP_CTL_EL02, 7L);
}
reg = mrs(CNTV_CTL_EL02);
if (reg == 0x5) {
uart_puts(" VIRT EL02 timer IRQ, masking");
msr(CNTV_CTL_EL02, 7L);
}
}
reg = mrs(SYS_APL_PMCR0);
if ((reg & (PMCR0_IMODE_MASK | PMCR0_IACT)) == (PMCR0_IMODE_FIQ | PMCR0_IACT)) {
uart_puts(" PMC IRQ, masking");