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https://github.com/AsahiLinux/m1n1
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m1n1.agx.render: Better t600x support
Signed-off-by: Asahi Lina <lina@asahilina.net>
This commit is contained in:
parent
bcd3d0274d
commit
05ece42eba
2 changed files with 66 additions and 46 deletions
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@ -219,6 +219,8 @@ class GPURenderer:
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self.work = []
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def submit(self, cmdbuf, wait_for=None):
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nclusters = 8
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work = GPUWork(self)
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self.work.append(work)
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@ -227,9 +229,15 @@ class GPURenderer:
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aux_fb = self.ctx.uobj.new_buf(0x20000, "Aux FB thing", track=False)
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work.add(aux_fb)
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deflake_1_size = 0x4000
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deflake_2_size = 0x4000
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deflake_3_size = 0x4000
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# t8103
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deflake_1_size = 0x540
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deflake_2_size = 0x280
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deflake_3_size = 0x20
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# t6002 - 9 times larger instead of 8? works with 8...
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deflake_1_size *= nclusters
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deflake_2_size *= nclusters
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deflake_3_size *= nclusters
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deflake_1 = self.ctx.uobj.new_buf(deflake_1_size, "Deflake 1", track=True)
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deflake_2 = self.ctx.uobj.new_buf(deflake_2_size, "Deflake 2", track=True)
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@ -238,37 +246,12 @@ class GPURenderer:
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work.add(deflake_2)
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work.add(deflake_3)
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#unk_tile_buf1 = self.ctx.uobj.new_buf(0xa000, "Unk tile buf 1", track=True)
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unk_tile_buf1 = self.ctx.uobj.new_buf(0xa0000, "Unk tile buf 1", track=True)
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unk_tile_buf2 = self.ctx.uobj.new_buf(0x80, "Unk tile buf 2", track=True)
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unk_tile_buf3 = self.ctx.uobj.new_buf(0xc80, "Unk tile buf 3", track=True)
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unk_tile_buf4 = self.ctx.uobj.new_buf(0x1400, "Unk tile buf 4", track=True)
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unk_tile_buf5 = self.ctx.uobj.new_buf(0x4000, "Unk tile buf 5", track=True)
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work.add(unk_tile_buf1)
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work.add(unk_tile_buf2)
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work.add(unk_tile_buf3)
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work.add(unk_tile_buf4)
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work.add(unk_tile_buf5)
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unk_buf = self.ctx.uobj.new(Array(0x800, Int64ul), "Unknown Buffer", track=False)
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work.add(unk_buf)
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unk_buf.val = [0, *range(2, 0x401), *(0x400 * [0])]
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unk_buf.push()
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depth_aux_buffer_addr = 0
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if cmdbuf.depth_buffer:
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depth_aux_buffer = self.ctx.uobj.new_buf(0x40000, "Depth Aux", track=True)
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work.add(depth_aux_buffer)
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depth_aux_buffer_addr = depth_aux_buffer._addr
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stencil_aux_buffer_addr = 0
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if cmdbuf.stencil_buffer:
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stencil_aux_buffer = self.ctx.uobj.new_buf(0x40000, "Stencil Aux", track=True)
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work.add(stencil_aux_buffer)
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stencil_aux_buffer_addr = stencil_aux_buffer._addr
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work.cmdbuf = cmdbuf
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self.frames += 1
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@ -332,7 +315,7 @@ class GPURenderer:
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tiling_params = TilingParameters()
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# rgn_header_size
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rgn_entry_size = 5
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tiling_params.size1 = align(rgn_entry_size * tiles_per_mtile_x * tiles_per_mtile_y, 4)
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tiling_params.size1 = align(rgn_entry_size * tiles_per_mtile_x * tiles_per_mtile_y // 4, 0x20)
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# PPP_MULTISAMPLECTL
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tiling_params.unk_4 = 0x88
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# PPP_CTRL
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@ -354,9 +337,23 @@ class GPURenderer:
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#tvb_something_size = 0x800 * tile_blocks
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#tvb_something = ctx.uobj.new_buf(tvb_something_size, "TVB Something", track=False).push()
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depth_aux_buffer_addr = 0
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if cmdbuf.depth_buffer:
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size = align_pot(max(width, tile_width)) * align_pot(max(height, tile_width)) // 32
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depth_aux_buffer = self.ctx.uobj.new_buf(size, "Depth Aux", track=True)
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work.add(depth_aux_buffer)
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depth_aux_buffer_addr = depth_aux_buffer._addr
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stencil_aux_buffer_addr = 0
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if cmdbuf.stencil_buffer:
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size = align_pot(max(width, tile_width)) * align_pot(max(height, tile_width)) // 32
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stencil_aux_buffer = self.ctx.uobj.new_buf(size, "Stencil Aux", track=False)
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work.add(stencil_aux_buffer)
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stencil_aux_buffer_addr = stencil_aux_buffer._addr
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#tvb_tilemap_size = 0x80 * mtile_stride
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tvb_tilemap_size = mtiles_x * mtiles_y * tiling_params.size1
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tvb_tilemap = ctx.uobj.new_buf(tvb_tilemap_size, "TVB Tilemap", track=False).push()
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tvb_tilemap_size = mtiles_x * mtiles_y * tiling_params.size1 * 4
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tvb_tilemap = ctx.uobj.new_buf(tvb_tilemap_size, "TVB Tilemap", track=True).push()
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work.tvb_tilemap_size = tvb_tilemap_size
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work.tvb_tilemap = tvb_tilemap
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work.add(tvb_tilemap)
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@ -367,6 +364,20 @@ class GPURenderer:
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tvb_heapmeta = ctx.uobj.new_buf(tvb_heapmeta_size, "TVB Heap Meta", track=False).push()
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work.add(tvb_heapmeta)
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unk_tile_buf1 = self.ctx.uobj.new_buf(tvb_tilemap_size * nclusters * 4, "Unk tile buf 1", track=True)
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print("tvb_tilemap_size", hex(tvb_tilemap_size))
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unk_tile_buf2 = self.ctx.uobj.new_buf(0x4 * nclusters, "Unk tile buf 2", track=True)
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#size = 0xc0 * nclusters
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size = 0xc80
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unk_tile_buf3 = self.ctx.uobj.new_buf(size, "Unk tile buf 3", track=True)
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unk_tile_buf4 = self.ctx.uobj.new_buf(0x280 * nclusters, "Unk tile buf 4", track=True)
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unk_tile_buf5 = self.ctx.uobj.new_buf(0x30 * nclusters, "Unk tile buf 5", track=True)
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work.add(unk_tile_buf1)
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work.add(unk_tile_buf2)
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work.add(unk_tile_buf3)
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work.add(unk_tile_buf4)
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work.add(unk_tile_buf5)
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##### Buffer stuff?
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# buffer related?
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@ -512,7 +523,8 @@ class GPURenderer:
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wc_3d.struct_1.unk_2d8 = 0x0
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wc_3d.struct_1.stencil_buffer_ptr2 = cmdbuf.stencil_buffer
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wc_3d.struct_1.stencil_buffer_ptr3 = cmdbuf.stencil_buffer
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wc_3d.struct_1.unk_2f0 = [0x0, 0x0, 0x0]
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wc_3d.struct_1.stencil_aux_buffer_ptr = stencil_aux_buffer_addr
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wc_3d.struct_1.unk_2f8 = [0x0, 0x0]
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wc_3d.struct_1.aux_fb_unk0 = 4 #0x8 # sometimes 4
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wc_3d.struct_1.unk_30c = 0x0
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wc_3d.struct_1.aux_fb = AuxFBInfo(0xc000, 0, width, height)
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@ -550,12 +562,15 @@ class GPURenderer:
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wc_3d.struct_2.depth_buffer_ptr2 = cmdbuf.depth_buffer
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wc_3d.struct_2.stencil_buffer_ptr1 = cmdbuf.stencil_buffer
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wc_3d.struct_2.stencil_buffer_ptr2 = cmdbuf.stencil_buffer
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wc_3d.struct_2.unk_68 = [0] * 4
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wc_3d.struct_2.unk_78 = [0] * 4
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wc_3d.struct_2.depth_aux_buffer_ptr1 = depth_aux_buffer_addr
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wc_3d.struct_2.unk_90 = 0
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wc_3d.struct_2.depth_aux_buffer_ptr2 = depth_aux_buffer_addr
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wc_3d.struct_2.unk_a0 = 0
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wc_3d.struct_2.unk_a8 = [0] * 4
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wc_3d.struct_2.depth_aux_buffer_ptr2 = depth_aux_buffer_addr
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wc_3d.struct_2.unk_b0 = 0
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wc_3d.struct_2.stencil_aux_buffer_ptr1 = stencil_aux_buffer_addr
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wc_3d.struct_2.unk_c0 = 0
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wc_3d.struct_2.stencil_aux_buffer_ptr2 = stencil_aux_buffer_addr
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wc_3d.struct_2.unk_d0 = 0
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wc_3d.struct_2.tvb_tilemap = tvb_tilemap._addr
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wc_3d.struct_2.tvb_heapmeta_addr = tvb_heapmeta._addr
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wc_3d.struct_2.unk_e8 = tiling_params.size1 << 24
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@ -796,27 +811,28 @@ class GPURenderer:
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wc_ta.struct_2.tvb_tilemap = tvb_tilemap._addr
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wc_ta.struct_2.unkptr_18 = unk_tile_buf1._addr
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wc_ta.struct_2.unkptr_20 = self.tvb_something._addr
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wc_ta.struct_2.tvb_heapmeta_addr = tvb_heapmeta._addr | 0x8000000000000000
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wc_ta.struct_2.tvb_heapmeta_addr = tvb_heapmeta._addr | 0x8000_0000_0000_0000
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wc_ta.struct_2.iogpu_unk_54 = 0x6b0003 # fixed
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wc_ta.struct_2.iogpu_unk_55 = 0x3a0012 # fixed
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wc_ta.struct_2.iogpu_unk_56 = 0x1 # fixed
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wc_ta.struct_2.unk_40 = unk_tile_buf2._addr | 0x4000000000000
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wc_ta.struct_2.unk_40 = unk_tile_buf2._addr | 0x4_0000_0000_0000
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wc_ta.struct_2.unk_48 = 0xa000 # fixed - maybe tvb_something_size?
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wc_ta.struct_2.unk_50 = 0x88 # fixed
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wc_ta.struct_2.tvb_heapmeta_addr2 = tvb_heapmeta._addr
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wc_ta.struct_2.unk_60 = 0x0 # fixed
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wc_ta.struct_2.unk_68 = 0xffffffffffffffff # ???
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wc_ta.struct_2.unk_68 = 0xffffffffffffffff
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#wc_ta.struct_2.unk_68 = 0xff << (8 * (self.buffer_mgr_slot % 8))
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wc_ta.struct_2.iogpu_deflake_1 = deflake_1._addr
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wc_ta.struct_2.iogpu_deflake_2 = deflake_2._addr
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wc_ta.struct_2.unk_80 = 0x1 # fixed
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wc_ta.struct_2.iogpu_deflake_3 = deflake_3._addr | 0x4000000000000 # check
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wc_ta.struct_2.iogpu_deflake_3 = deflake_3._addr | 0x4_0000_0000_0000 # check
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wc_ta.struct_2.encoder_addr = cmdbuf.encoder_ptr
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wc_ta.struct_2.unk_98 = [unk_tile_buf3._addr,
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unk_tile_buf4._addr]
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wc_ta.struct_2.unk_a8 = 0xa540 #0xa041 # fixed
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wc_ta.struct_2.unk_b0 = [0x0, 0x0, 0x0, 0x0, 0x0, 0x0] # fixed
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wc_ta.struct_2.pipeline_base = self.ctx.pipeline_base
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wc_ta.struct_2.unk_e8 = unk_tile_buf5._addr | 0x3000000000000000
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wc_ta.struct_2.unk_e8 = unk_tile_buf5._addr | 0x3000_0000_0000_0000
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wc_ta.struct_2.unk_f0 = 0x20 # fixed
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wc_ta.struct_2.unk_f8 = 0x8c60 # fixed
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wc_ta.struct_2.unk_100 = [0x0, 0x0, 0x0] # fixed
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@ -243,7 +243,8 @@ class Start3DStruct1(ConstructClass):
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"unk_2d8" / Int64ul,
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"stencil_buffer_ptr2" / Int64ul,
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"stencil_buffer_ptr3" / Int64ul,
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"unk_2f0" / Array(3, Int64ul),
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"stencil_aux_buffer_ptr" / Int64ul,
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"unk_2f8" / Array(2, Int64ul),
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"aux_fb_unk0" / Int32ul,
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"unk_30c" / Int32ul,
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"aux_fb" / AuxFBInfo,
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@ -277,12 +278,15 @@ class Start3DStruct2(ConstructClass):
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"depth_buffer_ptr2" / Int64ul,
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"stencil_buffer_ptr1" / Int64ul,
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"stencil_buffer_ptr2" / Int64ul,
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"unk_68" / Array(4, Int64ul),
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"unk_78" / Array(4, Int64ul),
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"depth_aux_buffer_ptr1" / Int64ul,
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"unk_90" / Int64ul,
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"depth_aux_buffer_ptr2" / Int64ul,
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"unk_a0" / Int64ul,
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"unk_a8" / Array(4, Int64ul),
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"depth_aux_buffer_ptr2" / Int64ul,
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"unk_b0" / Int64ul,
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"stencil_aux_buffer_ptr1" / Int64ul,
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"unk_c0" / Int64ul,
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"stencil_aux_buffer_ptr2" / Int64ul,
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"unk_d0" / Int64ul,
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"tvb_tilemap" / Int64ul,
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"tvb_heapmeta_addr" / Int64ul,
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"unk_e8" / Int64ul,
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