2021-06-10 10:40:48 +00:00
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#!/usr/bin/env python3
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# SPDX-License-Identifier: MIT
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import sys, pathlib
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sys.path.append(str(pathlib.Path(__file__).resolve().parents[1]))
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from m1n1.setup import *
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from m1n1 import asm
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2021-03-04 14:20:36 +00:00
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code_len = 12 * 16 * 8 + 4
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data_len = 8 * 16 * 8
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2021-05-25 10:55:51 +00:00
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if u.mrs(SPRR_CONFIG_EL1):
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u.msr(GXF_CONFIG_EL12, 0)
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u.msr(SPRR_CONFIG_EL12, 0)
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u.msr(GXF_CONFIG_EL1, 0)
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u.msr(SPRR_CONFIG_EL1, 0)
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2021-03-04 14:20:36 +00:00
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u.msr(HACR_EL2, 0)
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2021-05-25 10:55:51 +00:00
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hcr = HCR(u.mrs(HCR_EL2))
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hcr.TIDCP = 0
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hcr.TGE = 0
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u.msr(HCR_EL2, hcr.value)
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2021-03-04 14:20:36 +00:00
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u.inst(0xd5033fdf) # isb
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ACTLR_DEFAULT = 0xc00
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ACTLR_AFP = 1 << 5
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u.msr(ACTLR_EL1, ACTLR_DEFAULT | ACTLR_AFP)
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code_buffer = p.malloc(code_len)
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data_buffer = p.malloc(data_len)
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template = asm.ARMAsm("""
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mov x2, x0
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mrs x2, s3_0_c0_c0_0
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str x2, [x1], #8
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ret
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""", code_buffer)
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mov, mrs, st, ret = struct.unpack("4I", template.data)
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data = []
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BAD = 0xacce5515abad1dea
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2021-05-12 12:20:51 +00:00
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AUX = [
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ACTLR_EL1,
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ACTLR_EL2,
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AFSR0_EL1,
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AFSR0_EL2,
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AFSR1_EL1,
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AFSR1_EL2,
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AIDR_EL1,
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2021-05-13 11:10:51 +00:00
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AIDR2_EL1,
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2021-05-12 12:20:51 +00:00
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AMAIR_EL1,
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AMAIR_EL2,
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2021-05-13 11:10:51 +00:00
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APCTL_EL1,
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APSTS_EL1,
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2021-05-12 12:20:51 +00:00
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]
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2021-03-04 14:20:36 +00:00
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def test():
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2021-05-25 10:55:51 +00:00
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u.msr(SPRR_CONFIG_EL1, 1)
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u.msr(GXF_CONFIG_EL1, 1)
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u.msr(SPRR_CONFIG_EL12, 1)
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u.msr(GXF_CONFIG_EL12, 1)
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2021-03-04 14:20:36 +00:00
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for op1 in range(1 << 3):
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for CRn in (0b1011, 0b1111):
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mrs0 = mrs | (op1 << 16) | (CRn << 12)
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insns = []
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for CRm in range(1 << 4):
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for op2 in range(1 << 3):
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insns.extend((mov, mrs0 | (CRm << 8) | (op2 << 5), st))
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insns.append(ret)
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iface.writemem(code_buffer, struct.pack("<385I", *insns))
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p.dc_cvau(code_buffer, code_len)
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p.ic_ivau(code_buffer, code_len)
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2021-05-03 12:02:32 +00:00
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p.set_exc_guard(GUARD.SILENT | GUARD.SKIP)
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2021-03-04 14:20:36 +00:00
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p.el1_call(code_buffer, BAD, data_buffer)
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cnt = p.get_exc_count()
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data = iface.readmem(data_buffer, data_len)
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d = struct.unpack("<128Q", data)
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i = 0
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for CRm in range(1 << 4):
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for op2 in range(1 << 3):
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v = d[i]
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if v != BAD:
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2021-05-12 12:20:51 +00:00
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yield (3, op1, CRn, CRm, op2)
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2021-03-04 14:20:36 +00:00
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i += 1
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2021-05-12 12:20:51 +00:00
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for enc in AUX:
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try:
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2021-05-21 16:03:41 +00:00
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v = u.mrs(enc, call="el1", silent=True)
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2021-05-12 12:20:51 +00:00
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if v != BAD:
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yield enc
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except:
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continue
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2021-03-04 14:20:36 +00:00
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2021-05-25 10:55:51 +00:00
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u.msr(GXF_CONFIG_EL12, 0)
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u.msr(SPRR_CONFIG_EL12, 0)
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u.msr(GXF_CONFIG_EL1, 0)
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u.msr(SPRR_CONFIG_EL1, 0)
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2021-03-04 14:20:36 +00:00
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baseline = set(test())
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for bit in range(64):
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print()
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print ("## HACR_EL2[%d]" % bit)
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u.msr(HACR_EL2, 1<<bit)
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u.inst(0xd5033fdf) # isb
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new = set(test())
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added = new - baseline
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removed = baseline - new
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if added:
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print("Untraps:")
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2021-05-12 12:20:51 +00:00
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for enc in sorted(added):
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print(f"{sysreg_name(enc)} ({', '.join(str(i) for i in enc)})")
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2021-03-04 14:20:36 +00:00
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if removed:
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print("Traps:")
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2021-05-12 12:20:51 +00:00
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for enc in sorted(removed):
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print(f"{sysreg_name(enc)} ({', '.join(str(i) for i in enc)})")
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2021-03-04 14:20:36 +00:00
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2021-05-03 12:02:32 +00:00
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p.set_exc_guard(GUARD.OFF)
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