2022-05-31 11:15:17 +00:00
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#!/usr/bin/env python3
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# SPDX-License-Identifier: MIT
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import sys, pathlib
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import time
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sys.path.append(str(pathlib.Path(__file__).resolve().parents[1]))
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from m1n1.utils import *
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from enum import IntEnum
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from m1n1.setup import *
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from m1n1.hw.i2c import I2C
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class R_IRQ_MASK1(Register8):
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RING_PLUG = 0
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RING_UNPLUG = 1
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TIP_PLUG = 2
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TIP_UNPLUG = 3
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class E_DCID_GND_SEL(IntEnum):
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NONE = 0
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HS3 = 1
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HS4 = 2
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class E_DCID_Z_RANGE(IntEnum):
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NONE = 0
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UNK2 = 2
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UNK3 = 3
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class R_DCID_CTRL1(Register8):
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Z_RANGE = 2, 0, E_DCID_Z_RANGE
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class R_DCID_CTRL2(Register8):
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GND_SEL = 6, 4, E_DCID_GND_SEL
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class R_DCID_CTRL3(Register8):
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START = 0
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class R_DCID_STATUS(Register32):
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OVERALL = 9, 0
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DONE = 10
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U = 20, 11
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D = 30, 21
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class E_DEBOUNCE_TIME(IntEnum):
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T_0MS = 0b000
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T_125MS = 0b001
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T_250MS = 0b010
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T_500MS = 0b011
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T_750MS = 0b100
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T_1S = 0b101
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class R_TR_SENSE_CTRL(Register8):
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INV = 7
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UNK1 = 6
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FALLTIME = 5, 3, E_DEBOUNCE_TIME
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RISETIME = 2, 0, E_DEBOUNCE_TIME
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class R_TR_SENSE_STATUS(Register8):
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RING_PLUG = 0
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RING_UNPLUG = 1
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TIP_PLUG = 2
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TIP_UNPLUG = 3
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class R_MSM_BLOCK_EN3(Register8):
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TR_SENSE_EN = 3
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DCID_EN = 4
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2022-06-14 10:46:52 +00:00
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class R_HS_CLAMP_DISABLE(Register8):
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2022-05-31 11:15:17 +00:00
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HS_CLAMP_DISABLE = 0
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class E_SAMP_RATE(IntEnum):
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S_16KHZ = 1
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S_24KHZ = 2
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S_32KHZ = 3
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S_48KHZ = 4
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S_96KHZ = 5
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S_192KHZ = 6
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S_22K05HZ = 10
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S_44K1HZ = 12
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S_88K2HZ = 13
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S_176K4HZ = 14
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class R_CCM_SAMP_RATE(Register8):
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RATE = 7, 0, E_SAMP_RATE
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class R_DAC_CTRL1(Register8):
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HP_LOAD = 2 # maybe
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UNK2 = 4
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UNK3 = 5 # always set
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HIGH_V = 6
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class E_PULLDOWN_R(IntEnum):
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NONE = 0x0
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R_UNK8 = 0x8
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R_1K1OHMS = 0xc
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class R_DAC_CTRL2(Register8):
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PULLDOWN_R = 3, 0, E_PULLDOWN_R
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2022-06-14 10:46:52 +00:00
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class R_HSBIAS_SC_AUTOCTL(Register8):
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TIP_SENSE_EN = 5
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class E_TIP_SENSE_CTRL(IntEnum):
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DISABLED = 0b00
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DIG_INPUT = 0b01
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SHORT_DET = 0b11
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class R_TIP_SENSE_CTRL2(Register8):
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CTRL = 7, 6, E_TIP_SENSE_CTRL
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INV = 5
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class E_HSBIAS_CTRL(IntEnum):
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HI_Z = 0b00
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U_0V0 = 0b01
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U_2V0 = 0b10
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U_2V7 = 0b11
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class R_MISC_DET_CTRL(Register8):
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HSBIAS_CTRL = 2, 1, E_HSBIAS_CTRL
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class E_S0_DEBOUNCE_TIME(IntEnum):
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T_10MS = 0b000
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T_20MS = 0b001
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T_30MS = 0b010
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T_40MS = 0b011
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T_50MS = 0b100
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T_60MS = 0b101
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T_70MS = 0b110
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T_80MS = 0b111
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class R_MIC_DET_CTRL2(Register8):
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DEBOUNCE_TIME = 7, 5, E_S0_DEBOUNCE_TIME
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class R_MIC_DET_CTRL4(Register8):
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LATCH_TO_VP = 1
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class R_HS_SWITCH_CTRL(Register8):
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REF_HS3 = 7
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REF_HS4 = 6
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HSB_FILT_HS3 = 5
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HSB_FILT_HS4 = 4
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HSB_HS3 = 3
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HSB_HS4 = 2
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GNDHS_HS3 = 1
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GNDHS_HS4 = 0
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2022-05-31 11:15:17 +00:00
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class CS42L84Registers(RegMap):
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DEVID = irange(0x0, 5), Register8
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FREEZE = 0x6, Register8
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SW_RESET = 0x203, Register8
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IRQ_STATUS = irange(0x400, 3), Register8
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IRQ_MASK1 = 0x418, R_IRQ_MASK1
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IRQ_MASK2 = 0x419, Register8
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IRQ_MASK3 = 0x41a, Register8
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CCM_CTRL = irange(0x600, 4), Register8
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CCM_SAMP_RATE = 0x601, R_CCM_SAMP_RATE
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CCM_ASP_CLK_CTRL = 0x608, Register8
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PLL_CTRL = 0x800, Register8
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PLL_DIV_FRAC = irange(0x804, 3), Register8
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PLL_DIV_INT = 0x807, Register8
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PLL_DIVOUT = 0x808, Register8
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DCID_CTRL1 = 0x1200, R_DCID_CTRL1
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DCID_CTRL2 = 0x1201, R_DCID_CTRL2
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DCID_CTRL3 = 0x1202, R_DCID_CTRL3
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DCID_TRIM_OFFSET = 0x1207, Register8
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DCID_TRIM_SLOPE = 0x120a, Register8
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# R_pull = 1100 - (regval - 128)*2
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DCID_PULLDOWN_TRIM = 0x120b, Register8
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DCID_STATUS = 0x120c, R_DCID_STATUS
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# tip/ring sense
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TR_SENSE_CTRL1 = 0x1280, Register8
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TR_SENSE_CTRL2 = 0x1281, Register8
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RING_SENSE_CTRL = 0x1282, R_TR_SENSE_CTRL
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TIP_SENSE_CTRL = 0x1283, R_TR_SENSE_CTRL
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TR_SENSE_STATUS = 0x1288, R_TR_SENSE_STATUS
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2022-06-14 10:46:52 +00:00
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HSBIAS_SC_AUTOCTL = 0x1470, R_HSBIAS_SC_AUTOCTL
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WAKE_CTRL = 0x1471, Register8 # guess (cs42l42)
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TIP_SENSE_CTRL2 = 0x1473, R_TIP_SENSE_CTRL2 # guess (cs42l42)
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MISC_DET_CTRL = 0x1474, R_MISC_DET_CTRL # guess (cs42l42)
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MIC_DET_CTRL2 = 0x1478, R_MIC_DET_CTRL2
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MIC_DET_CTRL4 = 0x1477, R_MIC_DET_CTRL4
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MIKEY_DET_STATUS = irange(0x147c, 2), Register8
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MIKEY_DET_IRQ_MASK = irange(0x1480, 2), Register8
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MIKEY_DET_IRQ_STATUS = irange(0x1484, 2), Register8
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2022-05-31 11:15:17 +00:00
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2022-06-14 10:46:52 +00:00
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MSM_BLOCK_EN3 = 0x1802, R_MSM_BLOCK_EN3
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HS_SWITCH_CTRL = 0x1812, R_HS_SWITCH_CTRL
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HS_CLAMP_DISABLE = 0x1813, R_HS_CLAMP_DISABLE
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2022-05-31 11:15:17 +00:00
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ADC_CTRL = irange(0x2000, 4), Register8
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DAC_CTRL1 = 0x3000, R_DAC_CTRL1
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DAC_CTRL2 = 0x3001, R_DAC_CTRL2
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DACA_VOL_LSB = 0x3004, Register8
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DACA_VOL_MSB = 0x3005, Register8 # sign bit
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DACB_VOL_LSB = 0x3006, Register8
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DACB_VOL_MSB = 0x3007, Register8 # sign bit
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HP_VOL_CTRL = 0x3020, Register8
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HP_CLAMP_CTRL = 0x3123, Register8
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ASP_CTRL = 0x5000, Register8
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ASP_FSYNC_CTRL = irange(0x500f, 3), Register8
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ASP_DATA_CTRL = 0x5018, Register8
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ASP_RX_EN = 0x5020, Register8
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ASP_TX_EN = 0x5024, Register8
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ASP_RXSLOT_CH1_LSB = 0x5028, Register8
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ASP_RXSLOT_CH1_MSB = 0x5029, Register8
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ASP_RXSLOT_CH2_LSB = 0x502c, Register8
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ASP_RXSLOT_CH2_MSB = 0x502d, Register8
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ASP_TXSLOT_CH1_LSB = 0x5068, Register8
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ASP_TXSLOT_CH1_MSB = 0x5068, Register8
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class CS42L84:
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def __init__(self, bus, addr):
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self.regs = CS42L84Registers(self, 0)
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self.bus = bus
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self.addr = addr
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def write(self, regaddr, val, width=8):
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valbytes = val.to_bytes(width//8, byteorder="little")
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self.bus.write_reg(self.addr, regaddr, valbytes, regaddrlen=2)
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def read(self, regaddr, width=8):
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read = self.bus.read_reg(self.addr, regaddr, width//8, regaddrlen=2)
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return int.from_bytes(read, byteorder='little')
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def read_devid():
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pass
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def sense_Z():
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r = l84.regs
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2022-06-14 10:46:52 +00:00
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r.HS_CLAMP_DISABLE.set(HS_CLAMP_DISABLE=1)
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2022-05-31 11:15:17 +00:00
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r.DAC_CTRL2.set(PULLDOWN_R=E_PULLDOWN_R.R_1K1OHMS)
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r.DCID_CTRL1.set(Z_RANGE=E_DCID_Z_RANGE.UNK2)
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r.DCID_CTRL2.set(GND_SEL=E_DCID_GND_SEL.HS3)
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r.MSM_BLOCK_EN3.set(DCID_EN=1)
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r.DCID_CTRL3.set(START=0)
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r.DCID_CTRL3.set(START=1)
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while not r.DCID_STATUS.reg.DONE:
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pass
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reading = r.DCID_STATUS.reg.OVERALL
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offset_trim = r.DCID_TRIM_OFFSET.val - 128
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slope_trim = r.DCID_TRIM_SLOPE.val - 128
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pulldown_trim = r.DCID_PULLDOWN_TRIM.val - 128
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Y_overall = ((reading + 0.5) * 0.01086 - 1.0 / (1 - slope_trim * 0.001375)) \
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/ (614.0 + offset_trim * 0.125)
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Y_pulldown = 1.0 / (1100 - pulldown_trim*2)
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if Y_overall > Y_pulldown:
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Z_headphones = 1.0 / (Y_overall - Y_pulldown)
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else:
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Z_headphones = float('inf')
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r.MSM_BLOCK_EN3.set(DCID_EN=0)
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r.DAC_CTRL2.set(PULLDOWN_R=E_PULLDOWN_R.NONE)
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return Z_headphones
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def init_ring_tip_sense():
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2022-06-14 10:46:52 +00:00
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l84.regs.MIC_DET_CTRL4.set(LATCH_TO_VP=1)
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l84.regs.TIP_SENSE_CTRL2.set(CTRL=E_TIP_SENSE_CTRL.SHORT_DET)
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2022-05-31 11:15:17 +00:00
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l84.regs.RING_SENSE_CTRL.set(INV=1, UNK1=1,
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RISETIME=E_DEBOUNCE_TIME.T_125MS, FALLTIME=E_DEBOUNCE_TIME.T_125MS)
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l84.regs.TIP_SENSE_CTRL.set(INV=1,
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RISETIME=E_DEBOUNCE_TIME.T_500MS, FALLTIME=E_DEBOUNCE_TIME.T_125MS)
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l84.regs.MSM_BLOCK_EN3.set(TR_SENSE_EN=1)
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def wait_for_plug():
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while not l84.regs.TR_SENSE_STATUS.reg.TIP_PLUG:
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time.sleep(0.001)
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def wait_for_unplug():
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while l84.regs.TR_SENSE_STATUS.reg.TIP_UNPLUG:
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time.sleep(0.001)
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p.pmgr_adt_clocks_enable("/arm-io/i2c2")
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i2c2 = I2C(u, "/arm-io/i2c2")
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p.write32(0x2921f0010, 0x76a02) # invoke reset
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p.write32(0x2921f0010, 0x76a03) # out of reset
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l84 = CS42L84(i2c2, 0x4b)
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init_ring_tip_sense()
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while True:
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print("Waiting for plug... ", end=""); sys.stdout.flush()
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wait_for_plug()
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print("measuring... ", end=""); sys.stdout.flush()
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print(f"{sense_Z():.1f} ohms... ", end=""); sys.stdout.flush()
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wait_for_unplug()
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print("yanked")
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