mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-11-15 03:37:06 +00:00
299 lines
7.2 KiB
Python
299 lines
7.2 KiB
Python
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import sys, pathlib
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sys.path.append(str(pathlib.Path(__file__).resolve().parents[1]))
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from m1n1.setup import *
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from m1n1 import asm
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from m1n1.shell import run_shell
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from m1n1.gpiola import GPIOLogicAnalyzer
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class R_CTRL(Register32):
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RX_FIFO_RESET = 3
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TX_FIFO_RESET = 2
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RUN = 0
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class R_PIN(Register32):
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CS = 1
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KEEP_MOSI = 0
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class R_CONFIG(Register32):
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# impl: 002fb1e6
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IE_TX_COMPLETE = 21
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b19 = 19
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FIFO_THRESH = 18, 17
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# 0 = 8 bytes
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# 1 = 4 bytes
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# 2 = 1 byte
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# 3 = disabled
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WORD_SIZE = 16, 15
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# 0 = 8bit
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# 1 = 16bit
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# 2 = 32bit
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LSB_FIRST = 13
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b12 = 12
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IE_RX_THRESH = 8
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IE_RX_COMPLETE = 7
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MODE = 6, 5
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# 0 = polled
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# 1 = irq
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CPOL = 2
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CPHA = 1
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class R_STATUS(Register32):
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TX_COMPLETE = 22
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TXRX_THRESH = 1 # updated if MODE == 1
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RX_COMPLETE = 0
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class R_FIFO_STAT(Register32):
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LEVEL_RX = 31, 24
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RX_EMPTY = 20
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LEVEL_TX = 15, 8
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TX_FULL = 4
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class R_ISTATUS1(Register32):
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TX_XFER_DONE = 1
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RX_XFER_DONE = 0
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class R_ISTATUS2(Register32):
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TX_OVERFLOW = 17
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RX_UNDERRUN = 16
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TX_EMPTY = 9
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RX_FULL = 8
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TX_THRESH = 5
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RX_THRESH = 4
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class R_CLKDIV(Register32):
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DIVIDER = 10, 0 # SPI freq = CLK / (DIVIDER + 1)
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class R_INTER_DLY(Register32):
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DELAY = 15, 0
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# FIFO size: 16 bytes
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# backend FIFO: TX 2 bytes, RX 1 byte?
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class R_XFSTATUS(Register32):
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SR_FULL = 26
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SHIFTING = 20
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STATE = 17, 16
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UNK = 0
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class R_DIVSTATUS(Register32):
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COUNT2 = 31, 16
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COUNT1 = 15, 0
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class R_SHIFTCONFIG(Register32):
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OVERRIDE_CS = 24
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BITS = 21, 16
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RX_ENABLE = 11
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TX_ENABLE = 10
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CS_AS_DATA = 9
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AND_CLK_DATA = 8
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#? = 2 # needs to be 1 for RX to not break
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CS_ENABLE = 1
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CLK_ENABLE = 0
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class R_PINCONFIG(Register32):
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CLK_IDLE_VAL = 8
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KEEP_MOSI = 2
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NO_AUTO_CS = 1
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class R_DELAY(Register32):
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DELAY = 31, 16
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MOSI_VAL = 12
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SCK_VAL = 8
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SET_MOSI = 6
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SET_SCK = 4
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NO_INTERBYTE = 1
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ENABLE = 0
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class R_SCK_CONFIG(Register32):
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PERIOD = 31, 16
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PHASE1 = 9
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PHASE0 = 8
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RESET_TO_IDLE = 4
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class R_SCK_PHASES(Register32):
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PHASE1_START = 31, 16
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PHASE0_START = 15, 0
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class SPIRegs(RegMap):
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CTRL = 0x00, R_CTRL
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CONFIG = 0x04, R_CONFIG
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STATUS = 0x08, R_STATUS
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PIN = 0x0C, R_PIN
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TXDATA = 0x10, Register32
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RXDATA = 0x20, Register32
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CLKDIV = 0x30, R_CLKDIV
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RXCNT = 0x34, Register32
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INTER_DLY = 0x38, R_INTER_DLY
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TXCNT = 0x4C, Register32
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FIFO_STAT = 0x10C, R_FIFO_STAT
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IMASK1 = 0x130, R_ISTATUS1
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ISTATUS1 = 0x134, R_ISTATUS1
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IMASK2 = 0x138, R_ISTATUS2
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ISTATUS2 = 0x13c, R_ISTATUS2
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SHIFTCONFIG = 0x150, R_SHIFTCONFIG
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PINCONFIG = 0x154, R_PINCONFIG
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PRE_DLY = 0x160, R_DELAY
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SCK_CONFIG = 0x164, R_SCK_CONFIG
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POST_DLY = 0x168, R_DELAY
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SCK_PHASES = 0x180, R_SCK_PHASES
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UNK_PHASE = 0x18c, Register32 # probably MISO sample point
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XFSTATUS = 0x1c0, R_XFSTATUS
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DIVSTATUS = 0x1e0, R_DIVSTATUS
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p.smp_start_secondaries()
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p.set32(0x28e580208, 1<<31)
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p.clear32(0x28e580208, 1<<31)
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spi = u.adt["arm-io/spi3"].get_reg(0)[0]
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regs = SPIRegs(u, spi)
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mon.add(spi, 0x10)
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mon.add(spi + 0x30, 0x10)
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mon.add(spi + 0x40, 0x400)
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aic = u.adt["arm-io/aic"].get_reg(0)[0]
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mon.add(aic + 0x6800 + (1109 // 32) * 4, 4)
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gpio = u.adt["arm-io/gpio0"].get_reg(0)[0]
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mon.add(gpio, 0x1c8)
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mon.add(gpio+0x1e0, 0x300)
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mon.poll()
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m = GPIOLogicAnalyzer(u, "arm-io/gpio0",
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pins={"miso": 0x34, "mosi": 0x35, "clk": 0x36, "cs": 0x37},
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div=1, on_pin_change=False)
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#p.write32(spi + 0x100, 0xffffffff)
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regs.CTRL.val = 0xc
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regs.PIN.val = 0x2
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regs.CONFIG.val = 0x20 | (1<<15) | 6
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regs.CONFIG.val = 0x20 | (1<<15) | 4
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regs.CONFIG.val = 0x20 | (1<<15) | 2
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regs.CONFIG.val = 0x20 | (3<<15) | 0 | (0<<17)
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def try_all_bits():
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for i in range(0, 0x200, 4):
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v = p.read32(spi + i)
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for j in range(32):
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p.write32(spi + i, v ^ (1<<j))
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print(f"{i:4x}:{v:8x}:{j:2d} FIFO level:", regs.FIFO_LEVEL.reg.LEVEL_TX)
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mon.poll()
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p.write32(spi + i, v)
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regs.STATUS.val = 0xffffffff
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regs.ISTATUS1.val = 0xffffffff
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regs.ISTATUS2.val = 0xfffffff#f
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regs.CLKDIV.val = 0xfff
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regs.INTER_DLY.val = 0x1000
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regs.PINCONFIG.val = 0x101
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#p.write32(spi + 0x150, 0x80c07)
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p.write32(spi + 0x150, 0x88c07)
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print(hex(p.read32(spi + 0x150)))
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#p.write32(spi + 0x160, 0)
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p.write32(spi + 0x160, 0xfff0001)
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p.write32(spi + 0x168, 0)
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#p.write32(spi + 0x164, 0x06000210)
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#p.write32(spi + 0x180, 0x02000000)
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#p.write32(spi + 0x18c, 0x500)
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#regs.INTER_DLY2 = 0x20000001
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#p.write32(spi + 0x200, 0x11)
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m.regs = {
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"CTRL": (spi + 0x00, R_CTRL),
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"STATUS": (spi + 0x08, R_STATUS),
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"RXCNT": (spi + 0x34),
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"TXCNT": (spi + 0x4c),
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"FIFO_STAT": (spi + 0x10c, R_FIFO_STAT),
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"ISTATUS1": (spi + 0x134, R_ISTATUS1),
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"ISTATUS2": (spi + 0x13c, R_ISTATUS2),
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"XFSTATUS": (spi + 0x1c0),
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"DIVSTATUS": (spi + 0x1e0, R_DIVSTATUS)
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}
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m.start(300000, bufsize=0x80000)
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p.write32(0x28e0380c4, 0x80100000)
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data = b"Asahi Linux"
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for i in range(2):
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for j in data:
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regs.TXDATA.val = j
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regs.RXCNT.val = len(data)
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regs.TXCNT.val = len(data)
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regs.STATUS.val = 0xffffffff
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regs.ISTATUS1.val = 0xffffffff
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regs.ISTATUS2.val = 0xffffffff
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regs.PIN.val = 0x0
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regs.CTRL.val = 0x1
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#regs.TXDATA.val = 0xff
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#regs.TXDATA.val = 0xff
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i = 0
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while regs.TXCNT.val != 0:
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print(f"{regs.TXCNT.val:#x} {regs.FIFO_STAT.reg} {regs.STATUS.val:#x} {regs.ISTATUS2.val:#x} {p.read32(spi + 0x134):#x}")
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regs.STATUS.val = 0xffffffff
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#regs.ISTATUS1.val = 0xffffffff
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#regs.ISTATUS2.val = 0xffffffff
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#regs.CTRL.val = 0x0
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#time.sleep(0.1)
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#regs.CTRL.val = 0x1[
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print(hex(i))
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#p.write32(spi + i, 0xffffffff)
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#p.write32(spi + i, 0)
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i += 4
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if i > 0x100:
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break
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time.sleep(0.001)
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regs.PIN.val = 0x2
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#regs.PINCONFIG.val = 0x001
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#regs.PINCONFIG.val = 0x101
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#regs.PINCONFIG.val = 0x201
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#regs.PINCONFIG.val = 0x301
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print(f"{regs.RXCNT.val:#x} {regs.FIFO_STAT.reg} {regs.STATUS.val:#x} {regs.ISTATUS2.val:#x}")
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regs.STATUS.val = 0xffffffff
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regs.ISTATUS1.val = 0xffffffff
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regs.ISTATUS2.val = 0xffffffff
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while regs.FIFO_STAT.reg.LEVEL_RX:
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regs.RXDATA.val
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regs.CTRL.val = 0
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m.complete()
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m.show()
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def poll(count=1000):
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lval = None
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for i in range(count):
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pins = 0x35, 0x36, 0x37
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vals = [p.read32(gpio + 4 * pin) & 1 for pin in pins]
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if vals != lval:
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print(f"{i:6d}: {vals}")
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lval = vals
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mon.poll()
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#run_shell(globals(), msg="Have fun!")
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