2021-05-29 12:34:41 +00:00
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/* SPDX-License-Identifier: MIT */
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#include "adt.h"
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#include "i2c.h"
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#include "malloc.h"
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#include "pmgr.h"
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#include "types.h"
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#include "utils.h"
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#define PASEMI_FIFO_TX 0x00
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2021-10-10 14:15:32 +00:00
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#define PASEMI_TX_FLAG_READ BIT(10)
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#define PASEMI_TX_FLAG_STOP BIT(9)
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#define PASEMI_TX_FLAG_START BIT(8)
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2021-05-29 12:34:41 +00:00
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#define PASEMI_FIFO_RX 0x04
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2021-10-10 14:15:32 +00:00
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#define PASEMI_RX_FLAG_EMPTY BIT(8)
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2021-05-29 12:34:41 +00:00
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#define PASEMI_STATUS 0x14
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2021-10-10 14:15:32 +00:00
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#define PASEMI_STATUS_XFER_BUSY BIT(28)
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#define PASEMI_STATUS_XFER_ENDED BIT(27)
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2021-05-29 12:34:41 +00:00
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#define PASEMI_CONTROL 0x1c
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2021-10-10 14:15:32 +00:00
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#define PASEMI_CONTROL_CLEAR_RX BIT(10)
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#define PASEMI_CONTROL_CLEAR_TX BIT(9)
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2021-05-29 12:34:41 +00:00
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struct i2c_dev {
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uintptr_t base;
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};
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i2c_dev_t *i2c_init(const char *adt_node)
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{
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int adt_path[8];
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int adt_offset;
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adt_offset = adt_path_offset_trace(adt, adt_node, adt_path);
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if (adt_offset < 0) {
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printf("i2c: Error getting %s node\n", adt_node);
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return NULL;
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}
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u64 base;
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if (adt_get_reg(adt, adt_path, "reg", 0, &base, NULL) < 0) {
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printf("i2c: Error getting %s regs\n", adt_node);
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return NULL;
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}
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2022-01-10 17:16:57 +00:00
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if (pmgr_adt_power_enable(adt_node)) {
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printf("i2c: Error enabling power for %s\n", adt_node);
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2021-05-29 12:34:41 +00:00
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return NULL;
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}
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i2c_dev_t *dev = malloc(sizeof(*dev));
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if (!dev)
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return NULL;
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dev->base = base;
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return dev;
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}
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void i2c_shutdown(i2c_dev_t *dev)
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{
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free(dev);
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}
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static void i2c_clear_fifos(i2c_dev_t *dev)
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{
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set32(dev->base + PASEMI_CONTROL, PASEMI_CONTROL_CLEAR_TX | PASEMI_CONTROL_CLEAR_RX);
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}
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static void i2c_clear_status(i2c_dev_t *dev)
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{
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write32(dev->base + PASEMI_STATUS, 0xffffffff);
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}
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static void i2c_xfer_start_read(i2c_dev_t *dev, u8 addr, size_t len)
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{
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write32(dev->base + PASEMI_FIFO_TX, PASEMI_TX_FLAG_START | (addr << 1) | 1);
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write32(dev->base + PASEMI_FIFO_TX, PASEMI_TX_FLAG_READ | PASEMI_TX_FLAG_STOP | len);
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}
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static size_t i2c_xfer_read(i2c_dev_t *dev, u8 *bfr, size_t len)
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{
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for (size_t i = 0; i < len; ++i) {
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2022-02-06 04:54:49 +00:00
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u32 timeout = 5000;
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2021-11-18 13:18:27 +00:00
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u32 val;
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2021-05-29 12:34:41 +00:00
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2021-11-18 13:18:27 +00:00
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do {
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2021-05-29 12:34:41 +00:00
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val = read32(dev->base + PASEMI_FIFO_RX);
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2021-11-18 13:18:27 +00:00
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if (!(val & PASEMI_RX_FLAG_EMPTY))
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break;
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udelay(10);
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} while (--timeout);
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2021-10-10 14:15:32 +00:00
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if (val & PASEMI_RX_FLAG_EMPTY) {
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printf("i2c: timeout while reading (got %lu, expected %lu bytes)\n", i, len);
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2021-05-29 12:34:41 +00:00
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return i;
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2021-10-10 14:15:32 +00:00
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}
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2021-05-29 12:34:41 +00:00
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bfr[i] = val;
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}
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return len;
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}
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static int i2c_xfer_write(i2c_dev_t *dev, u8 addr, u32 start, u32 stop, const u8 *bfr, size_t len)
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{
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if (start)
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write32(dev->base + PASEMI_FIFO_TX, PASEMI_TX_FLAG_START | (addr << 1));
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for (size_t i = 0; i < len; ++i) {
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u32 data = bfr[i];
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if (i == (len - 1) && stop)
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data |= PASEMI_TX_FLAG_STOP;
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write32(dev->base + PASEMI_FIFO_TX, data);
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}
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if (!stop)
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return 0;
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2022-02-06 04:54:49 +00:00
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if (poll32(dev->base + PASEMI_STATUS, PASEMI_STATUS_XFER_BUSY, 0, 50000)) {
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2021-05-29 12:34:41 +00:00
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printf(
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2021-10-10 14:15:32 +00:00
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"i2c: timeout while waiting for PASEMI_STATUS_XFER_BUSY to clear after write xfer\n");
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2021-05-29 12:34:41 +00:00
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return -1;
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}
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return 0;
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}
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2021-10-10 14:38:33 +00:00
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int i2c_smbus_read(i2c_dev_t *dev, u8 addr, u8 reg, u8 *bfr, size_t len)
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2021-05-29 12:34:41 +00:00
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{
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2021-10-10 14:38:33 +00:00
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int ret = -1;
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2021-05-29 12:34:41 +00:00
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i2c_clear_fifos(dev);
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i2c_clear_status(dev);
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2021-11-18 13:15:13 +00:00
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if (i2c_xfer_write(dev, addr, 1, 0, ®, 1))
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2021-10-10 14:38:33 +00:00
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goto err;
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2021-05-29 12:34:41 +00:00
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i2c_xfer_start_read(dev, addr, len + 1);
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u8 len_reply;
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if (i2c_xfer_read(dev, &len_reply, 1) != 1)
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2021-10-10 14:38:33 +00:00
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goto err;
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2021-05-29 12:34:41 +00:00
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if (len_reply < len)
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printf("i2c: want to read %ld bytes from addr %d but can only read %d\n", len, addr,
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len_reply);
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if (len_reply > len)
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printf("i2c: want to read %ld bytes from addr %d but device wants to send %d\n", len, addr,
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len_reply);
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2021-10-10 14:38:33 +00:00
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ret = i2c_xfer_read(dev, bfr, min(len, len_reply));
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2021-10-10 14:15:32 +00:00
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2021-10-10 14:38:33 +00:00
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err:
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2022-02-06 04:54:49 +00:00
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if (poll32(dev->base + PASEMI_STATUS, PASEMI_STATUS_XFER_BUSY, 0, 50000)) {
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2021-10-10 14:15:32 +00:00
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printf("i2c: timeout while waiting for PASEMI_STATUS_XFER_BUSY to clear after read xfer\n");
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return -1;
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}
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2021-10-10 14:38:33 +00:00
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return ret;
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2021-05-29 12:34:41 +00:00
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}
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int i2c_smbus_write(i2c_dev_t *dev, u8 addr, u8 reg, const u8 *bfr, size_t len)
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{
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i2c_clear_fifos(dev);
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i2c_clear_status(dev);
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if (i2c_xfer_write(dev, addr, 1, 0, ®, 1))
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return -1;
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u8 len_send = len;
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if (i2c_xfer_write(dev, addr, 0, 0, &len_send, 1))
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return -1;
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if (i2c_xfer_write(dev, addr, 0, 1, bfr, len))
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return -1;
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return len_send;
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}
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int i2c_smbus_read32(i2c_dev_t *dev, u8 addr, u8 reg, u32 *val)
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{
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u8 bfr[4];
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if (i2c_smbus_read(dev, addr, reg, bfr, 4) != 4)
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return -1;
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*val = (bfr[0]) | (bfr[1] << 8) | (bfr[2] << 16) | (bfr[3] << 24);
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return 0;
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}
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int i2c_smbus_read16(i2c_dev_t *dev, u8 addr, u8 reg, u16 *val)
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{
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u8 bfr[2];
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if (i2c_smbus_read(dev, addr, reg, bfr, 2) != 2)
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return -1;
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*val = (bfr[0]) | (bfr[1] << 8);
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return 0;
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}
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int i2c_smbus_write32(i2c_dev_t *dev, u8 addr, u8 reg, u32 val)
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{
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u8 bfr[4];
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bfr[0] = val;
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bfr[1] = val >> 8;
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bfr[2] = val >> 16;
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bfr[3] = val >> 24;
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return i2c_smbus_write(dev, addr, reg, bfr, 4);
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}
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int i2c_smbus_read8(i2c_dev_t *dev, u8 addr, u8 reg, u8 *val)
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{
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if (i2c_smbus_read(dev, addr, reg, val, 1) != 1)
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return -1;
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return 0;
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}
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