mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-12-04 23:39:24 +00:00
212 lines
5.9 KiB
ArmAsm
212 lines
5.9 KiB
ArmAsm
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* For some reason GAS doesn't know about it, even with .cpu cortex-a57 */
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#define cpuactlr_el1 s3_1_c15_c2_0
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#define cpuectlr_el1 s3_1_c15_c2_1
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.macro RESET_CORE
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mov x0, #(1 << 63)
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msr cpuactlr_el1, x0 /* disable regional clock gating */
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isb
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mov x0, #3
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msr rmr_el3, x0
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isb
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dsb sy
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/* Nintendo forgot to copy-paste the branch instruction below. */
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1:
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wfi
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b 1b
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.endm
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.macro ERRATUM_INVALIDATE_BTB_AT_BOOT
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/* Nintendo copy-pasted https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/nvidia/tegra/common/aarch64/tegra_helpers.S#L312 */
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/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* The following comments are mine. */
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/*
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Enable invalidates of branch target buffer, then flush
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the entire instruction cache at the local level, and
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with the reg change, the branch target buffer, then disable
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invalidates of the branch target buffer again.
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*/
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mrs x0, cpuactlr_el1
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orr x0, x0, #1
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msr cpuactlr_el1, x0
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dsb sy
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isb
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ic iallu
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dsb sy
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isb
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mrs x0, cpuactlr_el1
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bic x0, x0, #1
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msr cpuactlr_el1, x0
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.rept 7
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nop /* wait long enough for the write to cpuactlr_el1 to have completed */
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.endr
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/* if the OS lock is set, disable it and request a warm reset */
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mrs x0, oslsr_el1
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ands x0, x0, #2
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b.eq 2f
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mov x0, xzr
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msr oslar_el1, x0
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RESET_CORE
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.rept 65
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nop /* guard against speculative excecution */
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.endr
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2:
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/* set the OS lock */
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mov x0, #1
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msr oslar_el1, x0
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.endm
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.section .warmboot.text.start, "ax", %progbits
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.align 4
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.global _start_warm
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_start_warm:
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/* mask all interrupts */
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msr daifset, #0xF
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/* Fixup hardware erratum */
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ERRATUM_INVALIDATE_BTB_AT_BOOT
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/* Acquire exclusive access to the common warmboot stack. */
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bl _ZN3ams6secmon26AcquireCommonWarmbootStackEv
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/* Set the stack pointer to the common warmboot stack address. */
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msr spsel, #1
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ldr x20, =0x7C0107C0
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mov sp, x20
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/* Perform warmboot setup. */
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bl _ZN3ams6secmon59SetupSocDmaControllersCpuMemoryControllersEnableMmuWarmbootEv
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/* Jump to the newly-mapped virtual address. */
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b _ZN3ams6secmon20StartWarmbootVirtualEv
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/* void ams::secmon::AcquireCommonWarmbootStack() { */
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/* NOTE: This implements critical section enter via https://en.wikipedia.org/wiki/Lamport%27s_bakery_algorithm */
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/* This algorithm is used because the MMU is not awake yet, so exclusive load/store instructions are not usable. */
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/* NOTE: Nintendo attempted to implement this algorithm themselves, but did not really understand how it works. */
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/* They use the same ticket number for all cores; this can lead to starvation and other problems. */
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.section .warmboot.text._ZN3ams6secmon26AcquireCommonWarmbootStackEv, "ax", %progbits
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.align 4
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.global _ZN3ams6secmon26AcquireCommonWarmbootStackEv
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_ZN3ams6secmon26AcquireCommonWarmbootStackEv:
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/* BakeryLock *lock = std::addressof(secmon::CommonWarmBootStackLock); */
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ldr x0, =_ZN3ams6secmon23CommonWarmbootStackLockE
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/* const u32 id = GetCurrentCoreId(); */
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mrs x8, mpidr_el1
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and x8, x8, #3
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/* lock->customers[id].is_entering = true; */
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ldrb w2, [x0, x8]
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orr w2, w2, #~0x7F
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strb w2, [x0, x8]
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/* const u8 ticket_0 = lock->customers[0].ticket_number; */
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ldrb w4, [x0, #0]
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and w4, w4, #0x7F
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/* const u8 ticket_1 = lock->customers[1].ticket_number; */
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ldrb w5, [x0, #1]
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and w5, w5, #0x7F
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/* const u8 ticket_2 = lock->customers[2].ticket_number; */
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ldrb w6, [x0, #2]
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and w6, w6, #0x7F
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/* const u8 ticket_3 = lock->customers[3].ticket_number; */
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ldrb w7, [x0, #3]
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and w7, w7, #0x7F
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/* u8 biggest_ticket = std::max(std::max(ticket_0, ticket_1), std::max(ticket_2, ticket_3)) */
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cmp w4, w5
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csel w2, w4, w5, hi
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cmp w6, w7
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csel w3, w6, w7, hi
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cmp w2, w3
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csel w2, w2, w3, hi
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/* NOTE: The biggest a ticket can ever be is 4, so the general increment is safe and 7-bit increment is not needed. */
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/* lock->customers[id] = { .is_entering = false, .ticket_number = ++biggest_ticket }; */
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add w2, w2, #1
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strb w2, [x0, x8]
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/* Ensure instructions aren't reordered around this point. */
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/* hw::DataSynchronizationBarrier(); */
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dsb sy
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/* hw::SendEvent(); */
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sev
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/* for (unsigned int i = 0; i < 4; ++i) { */
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mov w3, #0
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1:
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/* hw::SendEventLocal(); */
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sevl
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/* do { */
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2:
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/* hw::WaitForEvent(); */
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wfe
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/* while (lock->customers[i].is_entering); */
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ldrb w4, [x0, x3]
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tbnz w4, #7, 2b
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/* u8 their_ticket; */
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/* hw::SendEventLocal(); */
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sevl
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/* do { */
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2:
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/* hw::WaitForEvent(); */
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wfe
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/* their_ticket = lock->customers[i].ticket_number; */
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ldrb w4, [x0, x3]
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ands w4, w4, #0x7F
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/* if (their_ticket == 0) { break; } */
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b.eq 3f
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/* while ((their_ticket > my_ticket) || (their_ticket == my_ticket && id > i)); */
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cmp w2, w4
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b.hi 2b
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ccmp w8, w3, #0, eq
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b.hi 2b
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/* } */
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3:
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add w3, w3, #1
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cmp w3, #4
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b.ne 1b
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/* hw::DataMemoryBarrier(); */
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dmb sy
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ret
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